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PC87413 датащи(PDF) 61 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 61 Page - National Semiconductor (TI) |
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61 / 257 page ![]() 3.0 Device Architecture and Configuration (Continued) Revision 1.2 61 www.national.com 3.9 PARALLEL PORT (PP) CONFIGURATION 3.9.1 General Description The PC8741x Parallel Port supports all IEEE1284 standard communication modes: Compatibility (also known as Standard or SPP), Bidirectional (known also as PS/2), FIFO, EPP (also known as mode 4) and ECP (with an optional Extended ECP mode). The Parallel Port includes two groups of runtime registers, as follows (see Section 10.2 on page 222): • A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h) are used only in the Extended ECP mode. • A group of four registers, used only in the Extended ECP mode, accessed by a second level offset. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg- isters are used and which address bits are used for the base address. The FDC functional block registers are shown in Section 10.2 on page 222. All these registers are VDD powered. 3.9.2 Logical Device 1 (PP) Configuration Table 18 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Sec- tion 3.2.3 on page 40 for descriptions of the other configuration registers. All these registers are VDD powered. Table 18. Parallel Port Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 43). R/W VDD 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for A10) must be 0b. R/W VDD 02h 61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP mode 4 (EPP) or when using the Extended registers, bit 2 (A2) must also be 0b. R/W VDD 78h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 07h 71h Interrupt Type: Bits 7-2 are read only. Bit 1 is a read/write bit. Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation mode. This bit is set to 1 (level interrupt) in Extended mode and cleared (edge interrupt) in all other modes. R/W VDD 02h 74h DMA Channel Select. R/W VDD 04h 75h Report no second DMA assignment. RO VDD 04h F0h Parallel Port Configuration register. R/W VDD F2h |
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