PC87413 datasheet(47/257 Pages) NSC

47 / 257 page

3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.5.6

X-Bus I/O Map Lock (PC87416 and PC87417)

Protects the configuration of the X-Bus I/O address mapping.

Lock bit: LOCKIOMP in XIOCNF register (Device Configuration).

Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417).

Protected bits: All bits of the XIOCNF, XIOBA1H, XIOBA1L, XIOSIZE1, XIOBA2H, XIOBA2L and XIOSIZE2 registers (De-

vice Configuration).

3.5.7

X-Bus Memory Map Lock (PC87416 and PC87417)

Protects the configuration of the X-Bus memory address mapping.

Lock bit: LOCKMMP in XMEMCNF2 register (Device Configuration).

Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417).

Protected bits: All bits of the XMEMCNF1, XMEMCNF2, XMEMBAH, XMEMBAL and XMEMSIZE registers (Device Config-

uration).

3.5.8

X-Bus Chip Select Configuration Lock (PC87416 and PC87417)

Protects the configuration of the four X-Bus chip selects.

Lock bit: LOCKXSCF in XZM0 to XZM3 register (X-Bus Extension).

Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417).

Protected bits: All bits of the XBCNF, XZCNF0 to XZCNF3 and XZM0 to XZM3 registers, except the WRSTAT bit of the

XZM0-XZM3 registers (X-Bus Extension).

3.5.9

X-Bus Host Protection Lock (PC87416 and PC87417)

Protects the Host Protection configuration bits for each memory block of XCS0 and XCS1 chip selects.

Lock bit: LOCKXHP in all 16 indexes of the HAP0 and HAP1 registers (X-Bus Extension).

Unlock bit: UNLOCKX in ACBLKCTL register (ACCESS.bus Interface - PC87417).

Protected bits: HWRP and HRDP bits of all 16 indexes of the HAP0 and HAP1 registers (X-Bus Extension).

3.5.10

SWC Timers Protection Lock

Protects the access to the reset of the Power Active timers in the SWC module.

Lock bit: LOCK_TMRRST in PWTMRCTL register (System Wake-Up Control).

Unlock bit: UNLOCKS in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417).

Protected bits: All bits of the PWTMRCTL register (System Wake-Up Control).

3.5.11

SWC Sleep State Configuration Lock

Protects the Sleep Type encoding configuration in the SWC module.

Lock bit: LOCK_SLP_ENC in SLP_ST_CFG register (System Wake-Up Control).

Unlock bit: UNLOCKS in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417).

Protected bits: All bits of the SLP_ST_CFG and S0_SLP_TYP to S5_SLP_TYP registers (System Wake-Up Control).

3.5.12

CMOS RAM Access Lock

Protects access lock configuration bits of the CMOS Standard and Extended RAM.

Lock bits: BLSTR, BLRWR, BLEXRWR, BLEXRRD and BLEXR in RLR register (Real-Time Clock).

Unlock bit: UNLOCKR in ACBLKCTL register (ACCESS.bus Interface - PC87413 and PC87417).

Protected bits: Standard and Extended CMOS RAM bits for read and/or write access by the host (Real-Time Clock; see Sec-

tion 3.16.3 on page 88).

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