PC87413 datasheet(120/257 Pages) NSC

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6.0 ACCESS.bus Interface (Continued)

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Revision1.2

The ACCESS.bus protocol allows a General Call address to be sent to all slaves connected to the bus. The first byte sent

specifies the General Call address (00h) and the second byte specifies the meaning of the general call (“Reset and write

programmable part of slave address by hardware”—06h). When a 00h-followed-by-a-06h transaction is detected, the

PC8741x device resets the ACCESS.bus Interface logic and the data registers (except for the configuration registers) and

reloads the default slave address.

6.2.7

Arbitration on the Bus

Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is

initially determined according to address bits and clock cycle. If more than one master try to address the same slave, data

comparisons determine the outcome of this arbitration. A master device immediately aborts a transaction if the value sam-

pled on the ACBDAT line differs from the value internally driven by the device. (An exception to this rule is ACBDAT while

the master is receiving data. The lines may be held low by the slave without causing an abort.)

The ACBCLK signal is monitored by the master for clock synchronization and to allow the slave to stall the bus. The actual

clock period is set either by the master with the longest clock period or by the slave stall period. The maximum allowed “cu-

mulative clock low extend time” of a slave device (per transaction) is defined in Section 11.5.6 on page 246. The clock high

period is determined by the master with the shortest clock high period; however, it must not be longer than the value defined

in Section 11.5.6.

When an abort occurs during the address transmission, the master that identifies the conflict must release the bus, switch

to Slave mode and continue to sample ACBDAT to check if it is being addressed by the winning master on the bus.

If the PC8741x device detects that ACBCLK is held low longer than the maximum allowed time, it aborts the current trans-

action and sets the LOWCKTO bit in the ACBCST register (see Section 6.3.2 on page 127).

6.2.8

Packet Error Check (PEC)

The Packet Error Checking mechanism complies with Revision 1.1 of the SMBus Specification. It consists of appending an

error check byte to the end of each transaction (before the Stop condition).

The PC8741x devices are capable of communicating with all masters, whether or not they implement the PEC.

Master PEC Assessment

After reset, a master supporting the PEC feature performs the following sequence:

1. Read (without PEC) the ACBCST register of the PC8741x slave device.

2. Check the PECAVAIL bit (bit 0 of the register), which indicates the PEC slave support (for the PC8741x devices, this bit

is always ‘1’).

3. Read (with PEC) the ACBCST register and check for its correctness.

4. Register the PC8741x slave device as PEC compliant.

All subsequent transactions between the master and the PEC-compliant slave include the PEC byte. During write transac-

tions, the master provides the PEC of the transmitted data. During read transactions, the master checks the received data

using the PEC supplied by the slave. In both cases, the master supplies the number of ACBCLK cycles required for PEC

support. If the master does not supply these clock cycles, the PC8741x device considers that PEC is not supported during

the current transaction (i.e., there is no error condition).

Slave PEC Support

The PC8741x device provides PEC support when the master also requires it. However, the PC8741x device always calcu-

lates the PEC value of the incoming or outgoing data.

Start

Condition

Stop

Condition

ACBDAT

ACBCLK

1 - 7

Slave

R/W ACK

Data

ACK

Data

ACK

Figure 34. A Complete ACCESS.bus Data Transaction

Address

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