PC87413 datasheet(93/257 Pages) NSC

93 / 257 page

5.0 X-Bus Extension (Continued)

Revision 1.2

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There are two X-Bus address modes:

Normal Address mode - A signal is assigned for each address line (only XA11-XA0 are available at the device pins)

and a non-multiplexed address data bus is used. In this mode, only address signals 0 through 11 are generated.

Latched Address mode - The number of pins used for outputting the address is reduced. The address lines are mul-

tiplexed with the data bus. External latches may be used to generate address signals from the multiplexed bus. These

address signals are required to access memory and I/O devices. In this mode address, signals 0 through 27 are gen-

erated, allowing access to memory in excess of 1 Mbyte.

There are two X-Bus transaction modes:

Mode 0 - The X-Bus transactions are ISA-like, using separate read and write signals. XWR_XRW functions as the

write signal (XWR); XRD_XEN functions as the read signal (XRD). The following speed levels are available for

Mode 0, X-Bus transactions:

— Normal

— Fast

— Turbo

Mode 1 - The X-Bus transactions are read/write and enable controlled transactions, using XWR_XRW as the read

and write signal (XRW) and XRD_XEN as the enable signal (XEN). When XWR_XRW is high, it identiﬁes a read

transaction; when low, it identiﬁes a write transaction.

5.2.1

Transaction Clock

X-Bus access timing is referenced to an internal clock referred to as CLK or “the clock”. Transactions are described in terms

of this clock and the AC speciﬁcations are also deﬁned relative to it. This provides an easy way for calculating the timing

during system design. Note that the system interface is optimized for an asynchronous interface. For hints on how to use the

asynchronous interface, refer to the usage hints in Section 5.5 on page 115.

X-Bus Clock:

For transactions triggered by the LPC bus, the clock is an internal version of the LPC clock (i.e., it has the same fre-

quency but may have some phase delay).

For transactions driven by the ACCESS.bus (PC87417), the clock is the Standby clock as deﬁned in Section 2.3.1 on

page 36.

5.2.2

Programmable Range Chip Select

The PC8741x has four chip-select signals (XCS3-0) to control the X-Bus accesses to off-chip devices. The PC8741x X-Bus

functional block enables flexible association of these chip selects with I/O and memory address ranges in the LPC address

space. The Zone Mapping field of the X-Bus Select Configuration registers defines the decoded address range(s) to which

the specific XCSn signal responds. In addition, the X-Bus Configuration register enables specifying the access time for each

select signal via bits that control the fixed wait and variable wait cycles (using the XRDY input).

If the chip-select signal setting results in a conflict in which one or more selects are configured for the same zone, XCS0 has

the highest priority and XCS3 has the lowest. The XCSn signal with the lower priority remain inactive and their Select Con-

figuration register setting is ignored. For zones that are not associated with one of the chip-select signals, the X-Bus does

not respond to LPC transactions.

In addition, X-Bus transactions may be generated in response to a request from the ACCESS.bus (PC87417). In such a

case, the target select signal (XCS3) and the offset address are specified in the ACCESS.bus protocol. See Section 6.2.9

on page 121 for the specification of ACCESS.bus operation.

5.2.3

LPC and FWH Address-to-X-Bus Address Translation

The BIOS memory on the LPC bus can occupy one of three regions in the memory space (see Table 28 on page 76). Ad-

dress translation between the LPC bus address and the X-Bus is performed as follows:

I/O Transactions. The 16-bit address received from the LPC bus is used to decode the different I/O zones described in

Section 3.15.2 on page 75. The address is then left-padded with zeroes (address lines 16 through 27) to create the 28-line

input address to the X-Bus Extension functional block.

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