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PC87413 датащи(PDF) 81 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 81 Page - National Semiconductor (TI) |
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81 / 257 page ![]() 3.0 Device Architecture and Configuration (Continued) Revision 1.2 81 www.national.com 3.15.8 X-Bus I/O Base Address 2 High Byte Register (XIOBA2H) This register describes the high byte of the Base Address for User-Defined I/O zone blocks 2 and 3, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well:VSB Location:Index F4 Type: R/W or RO 3.15.9 X-Bus I/O Base Address 2 Low Byte Register (XIOBA2L) This register describes the low byte of the Base Address for User-Defined I/O zone blocks 2 and 3, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well:VSB Location:Index F5h Type: R/W or RO Bit 76543210 Name IOBA2H Reset 00000000 Bit Description 7-0 IOBA2H (I/O User-Defined Zone Base Address 2 High). Defines the upper eight bits of the User-Defined I/O blocks 2 and 3 base address. The base address must be aligned on the selected block size. Bit 76543210 Name IOBA2L Reset 00000000 Bit Description 7-0 IOBA2L (I/O User-Defined Zone Base Address 2 Low). Defines the lower eight bits of the user-defined I/O blocks 2 and 3 base address. The base address must be aligned on the selected block size. |
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