PC87413 datasheet(9/257 Pages) NSC

9 / 257 page

Table of Contents (Continued)

Revision 1.2

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3.11

SERIAL PORT 1 CONFIGURATION ........................................................................................ 65

3.11.1

General Description ..................................................................................................... 65

3.11.2

Logical Device 3 (SP1) Configuration .......................................................................... 65

3.11.3

Serial Port 1 Configuration Register ............................................................................ 66

3.12

SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION .................................................... 67

3.12.1

General Description ..................................................................................................... 67

3.12.2

Logical Device 4 (SWC) Configuration ........................................................................ 67

3.13

KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION .................................... 68

3.13.1

General Description ..................................................................................................... 68

3.13.2

Logical Devices 5 and 6 (Mouse and Keyboard) Configuration .................................. 68

3.13.3

KBC Configuration Register ........................................................................................ 69

3.14

GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION ......................... 70

3.14.1

General Description ..................................................................................................... 70

3.14.2

Logical Device 7 (GPIO) Configuration ....................................................................... 71

3.14.3

GPIO Pin Select Register (GPSEL) ............................................................................. 72

3.14.4

GPIO Pin Configuration Register 1 (GPCFG1) ........................................................... 72

3.14.5

GPIO Event Routing Register (GPEVR) ...................................................................... 74

3.14.6

GPIO Pin Configuration Register 2 (GPCFG2) ........................................................... 74

3.15

X-BUS CONFIGURATION ........................................................................................................75

3.15.1

Logical Device F (X-Bus) Configuration ...................................................................... 75

3.15.2

X-Bus I/O Range Programming ................................................................................... 75

3.15.3

X-Bus Memory Range Programming ........................................................................... 76

3.15.4

X-Bus I/O Configuration Register (XIOCNF) ............................................................... 78

3.15.5

X-Bus I/O Base Address 1 High Byte Register (XIOBA1H) ......................................... 79

3.15.6

X-Bus I/O Base Address 1 Low Byte Register (XIOBA1L) .......................................... 80

3.15.7

X-Bus I/O Size 1 Configuration Register (XIOSIZE1) .................................................. 80

3.15.8

X-Bus I/O Base Address 2 High Byte Register (XIOBA2H) ......................................... 81

3.15.9

X-Bus I/O Base Address 2 Low Byte Register (XIOBA2L) .......................................... 81

3.15.10 X-Bus I/O Size 2 Configuration Register (XIOSIZE2) ................................................. 82

3.15.11 X-Bus Memory Configuration Register 1 (XMEMCNF1) ............................................ 83

3.15.12 X-Bus Memory Configuration Register 2 (XMEMCNF2) ............................................ 84

3.15.13 X-Bus Memory Base Address High Byte Register (XMEMBAH) ................................ 85

3.15.14 X-Bus Memory Base Address Low Byte Register (XMEMBAL) ................................. 85

3.15.15 X-Bus Memory Size Configuration Register (XMEMSIZE) ......................................... 86

3.15.16 X-Bus IRQ Mapping Register (XIRQMAP) ................................................................. 86

3.16

REAL TIME CLOCK (RTC) CONFIGURATION ....................................................................... 87

3.16.1

General Description ..................................................................................................... 87

3.16.2

Logical Device 10 (RTC) Configuration ....................................................................... 87

3.16.3

RAM Lock Register (RLR) ........................................................................................... 88

3.16.4

Date-of-Month Alarm Register Offset (DOMAO) ......................................................... 89

3.16.5

Month Alarm Register Offset (MONAO) ...................................................................... 89

3.16.6

Century Register Offset (CENO) ................................................................................. 89

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