PC87413 datasheet(37/257 Pages) NSC

37 / 257 page

2.0 Power, Reset and Clocks (Continued)

Revision 1.2

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The Frequency Multiplier generates either a 40 MHz or a 48 MHz clock out of the 32.768 KHz clock from the on-chip crystal

oscillator (which is a part of the RTC module; see Section 8.2.2 on page 142). The frequency is selected by the value read

at VSB Power-Up reset from the CKIN48 strap input pin (available for read in the CKIN48 bit of the CLOCKCF register; see

Section 3.7.10 on page 56):

• A strap value of ‘0’ configures the PC8741x device to work without a clock signal that is connected to the CLKIN pin and

to generate a 48 MHz internal clock. This clock is used for the Standby and Output clock domains and is also selected

for the Legacy modules.

• A strap value of ‘1’ configures the PC8741x device to work with a 48 MHz clock signal connected to the CLKIN pin and

to generate a 40 MHz internal clock. This clock is used only for the Standby and Output clock domains. The 48 MHz

input clock is selected for the Legacy modules.

The internal clock generated by the Frequency Multiplier is divided by two and used as the basic clock for the ACCESS.bus Inter-

face and X-Bus Extension modules. In addition, it is scaled-down by a programmable divider and generates the HFCKOUT signal.

On power-up, when VSB is applied, the Frequency Multiplier waits for the 32.768 KHz clock to stabilize before it starts

generating the internal clock. The multiplier output clock is frozen to a low level until the multiplier provides a stable clock

signal that meets all requirements. Then the multiplier output clock starts toggling.

The status of the internal clock is indicated by the CKVALID bit of the CLOCKCF register. While either the on-chip crystal

oscillator or the Frequency Multiplier is stabilizing, this bit is 0, indicating an internal clock frozen at low level. When the in-

ternal clock starts toggling, this bit is set to 1. The software must activate (enable) the Legacy modules (Serial Ports, Parallel

Port, FDC, KBC) only after the CKVALID bit is set.

The programmable divider scales down the frequency of the internal clock according to the CKIN48 strap and the HFCKDV

field of the CLOCKCF register (see Section 3.7.10 on page 56), as shown in Table 7.

During frequency transitions caused by software changing the HFCKDIV field value, the output clock is guaranteed to be

glitch free. The high or low level of the clock signal is stable for at least half of the shortest cycle between the previous and

the new frequency.

When the alternate function (GPIO07) is selected for the device pin (see Section 3.7.3 on page 50) or if the HFCKDIS bit in

the CLOCKCF register is set, the programmable divider is disabled to save power. When the programmable divider is dis-

abled by setting the HFCKDIS bit, HFCKOUT is stopped at low level.

Speciﬁcations

Frequency Multiplier wake-up time is 33 msec (maximum). This is measured from a valid VSB or a valid 32.768 KHz clock

until the internal clock is stable. Tolerance (long term deviation) of the multiplier output clock, relative to the 32.768 KHz clock,

±110 ppm. Total tolerance is therefore ± (input clock tolerance + 110 ppm). Cycle-by-cycle variance is 0.4 nsec (maximum).

2.3.3

Low Frequency Clock

This clock output is obtained by selecting to the LFCKOUT pin either the 32.768 KHz clock or a 1 Hz signal (generated by

the RTC). The LFCKSEL bit in the CLOCKCF register (see Section 3.7.10 on page 56) is responsible for the selection. The

transition from one clock source to the other is not guaranteed to be glitch free.

Table 7. HFCKOUT Frequency Selection

HFCKOUT Frequency

HFCKDIV Field

Divisor

Default

CKIN48 = 0

CKIN48 = 1

Bit 2

Bit 1

Bit 0

48 MHz

40 MHz1

1. The actual value is 40.004 MHz.

40 MHz at CKIN48=1

24 MHz

20 MHz

2. The output signal, generated using all the division ratios (divisors), has an accurate 50% duty cycle.

24 MHz at CKIN48=0

16 MHz

13.333 MHz

12 MHz

10 MHz

8 MHz

6.667 MHz

6 MHz

5 MHz

4 MHz

3.333 MHz

3 MHz

2.5 MHz

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