PC87413 datasheet(119/257 Pages) NSC

119 / 257 page

6.0 ACCESS.bus Interface (Continued)

Revision 1.2

119

www.national.com

6.2.5

Acknowledge after Every Byte Rule

According to this rule, the master generates an acknowledge clock pulse after each byte transfer and the receiver (master

or slave) sends an acknowledge signal after every byte received. There are two exceptions to this rule:

• When the master is the receiver, it must indicate to the slave transmitter the end of the expected data by not acknowl-

edging (NACK) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock

pulse (generated by the master), but the ACBDAT line is not pulled down.

• When a problem has occurred in the slave receiver, it sends a NACK to indicate that it did not accept the previous data

byte or cannot accept additional data bytes.

The NACK indicates an error in data reception (by slave or master) and a request to repeat the ACCESS.bus transaction.

6.2.6

Addressing Transfer Formats

Each device on the bus has a unique address. The PC8741x device starts a slave address set-up process if one of the fol-

lowing occurs:

• AV

SB Power-Up reset is activated by VSB going up: in this case, the ACBSA strap value is also sampled (see Section

2.2.2 on page 34).

• A broadcast transaction to the General Call address with a “Reset and write programmable part of slave address by hard-

ware” command is received over the ACCESS.bus (see below).

During the slave address set-up process, the PC8741x device performs the following actions in the order listed:

1. Checks the value of the ACBSADD field in the ACBCF register (see Section 3.7.11 on page 57); if the value of the bits

is valid (not zero), the value is adopted and the other two actions are ignored.

2. Checks the value of the ACBSA strap sampled at the VSB Power-Up reset.

3. Adopts one of the two fixed values (see Section 1.4.11 on page 29) for its slave address, according to the ACBSA value.

Before any data is transmitted, the master transmits the address of the target slave. The slave must send an acknowledge

signal on the ACBDAT line once it recognizes its address.

The address consists of the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the

eighth bit (which is sent after the address).

When the address is sent, each device in the system compares this address with its own. If there is a match, the device

considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the

device acts either as a transmitter or a receiver. The combination of the 7-bit address and the R/W bit is used in this docu-

ment to define the slave address as a write address (even) and a read address (odd) pair.

A low-to-high transition during a ACBCLK high period indicates the Stop Condition and ends the transaction of ACBDAT

(see Figure 34).

Start Condition

ACBCLK

12 3 - 6

Transmitter Stays Off Bus

During Acknowledge Clock

Acknowledge

Signal From Receiver

Data Output

by Transmitter

Data Output

by Receiver

Figure 33. ACCESS.bus Acknowledge Cycle

PC87413 датащи(PDF) 119 Page - National Semiconductor (TI)

PC87413 датащи(HTML) 119 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL