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PC87413 датащи(PDF) 31 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 31 Page - National Semiconductor (TI) |
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31 / 257 page ![]() 1.0 Signal/Pin Connection and Description (Continued) Revision 1.2 31 www.national.com System Wake-Up Control (SWC) PWBTIN 36 PU25 SLBTIN 35 PU25 PWBTOUT 49 PU25 Note 2 General-Purpose Input/Output (GPIO) Ports GPIO00-04, 05-06, 07 124-128, 9-10, 13 PU25 Programmable3 GPIOE10-17 1-8 PU25 Programmable3 GPIO20-25, 26-27 14-19, 22-23 PU25 Programmable3 GPIO30-37 24-31 PU25 Programmable3 GPIOE40-41, 42, 43-47 20-21, 35, 49-53 PU25 Programmable3 GPIO50-52, 53, 54, 55 36-38, 45, 54, 56 PU25 Programmable3 GPO60-62, 63, 64 32-34, 48, 55 PU50 Programmable3,4 Strap Configuration BADDR 100 PD110 Strap5 TRIS 97 PD60 Strap5 CKIN48 55 PD110 Strap6 XCNF2-0 (PC87416, PC87417) 32-34 PD110 Strap6 ACBSA (PC87413, PC87417) 48 PD110 Strap6 1. Default at reset: disabled. 2. Disabled when VDD is off. 3. See Table 26 on page 73 for default value at reset (0 = PU disabled, 1 = PU enabled). 4. Disabled during VSB Power-Up reset. 5. Active only during VDD Power-Up reset. 6. Active only during VSB Power-Up reset. Table 3. Internal Pull-Up and Pull-Down Resistors (Continued) Signal Pin/s Type Comments |
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