PC87413 datasheet(92/257 Pages) NSC

92 / 257 page

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Revision 1.2

5.0

X-Bus Extension

This section is relevant only for the PC87416 and PC87417. In the PC87413 and PC87414, all X-Bus Extension bits

and signals that influence other modules are at their default value.

5.1

OVERVIEW

The PC8741x provides an X-Bus extension to the LPC bus or ACCESS.bus to enable the connection of external 8-bit

memories or peripherals through the X-Bus’s ISA-like interface. A single read/write line and an enable pin replace the ISA-

like protocol. The decode logic, described in Section 3.15 on page 75, defines the addresses for which the X-Bus generates

transactions that occur in the I/O address space and memory address space or in the FWH memory address space. Using

the X-Bus Interface, the PC8741x serves as a bridge for such transactions over the X-Bus. Figure 12 is a block diagram of

the X-Bus bridging function. For details on the decoder functions, see Section 3.15 on page 75. All other functions are de-

scribed in detail in this section.

Figure 12. X-Bus Extension Block Diagram

The PC8741x supports one IRQ input: XIRQ. This pin may be used to support external legacy devices that are connected

on the X-Bus. The interrupt from this pin can be routed to any one of 15 host IRQs. The IRQ input is mapped by the X-Bus

XIRQ Mapping register at FCh. The XIRQC register enables the user to define the interrupt as active high or low and to route

it to a wake-up event.

5.2

X-BUS TRANSACTIONS

The X-Bus extension supports 8-bit I/O or Memory read/write cycles.

The zone mapping of the chip-select signals determines how X-Bus read and write cycles correspond to memory and I/O

LPC bus cycles. The zone mapping to a select signal (XCS3-0) must be enabled in order for the zone to respond to LPC

transactions. However, when the chip-select signal is not required by an off-chip device, multiplexing the chip select to a pin

is not necessary.

LPC

Bus

X-Bus

Configuration

I/O

Address

Memory

Address

Decoder

Bus

Cycle

Generator

XCS0

XCS2

XA11-0

X-Bus Interface

Device Architecture Module

XWR_XRW

XSTB2-0

XRDY

XD7-0

IRQ Router

IRQ

Serializer

XIRQ

XCNF2-0

XRD_XEN

XCS3

XCS1

ACCESS.bus

SERIRQ

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