PC87413 datasheet(10/257 Pages) NSC

10 / 257 page

Table of Contents (Continued)

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Revision 1.2

4.0

LPC Bus Interface

4.1

OVERVIEW ............................................................................................................................... 90

4.2

LPC TRANSACTIONS ............................................................................................................... 90

4.3

CLKRUN FUNCTIONALITY ...................................................................................................... 91

4.4

INTERRUPT SERIALIZER ........................................................................................................ 91

5.0

X-Bus Extension

5.1

OVERVIEW ............................................................................................................................... 92

5.2

X-BUS TRANSACTIONS ...........................................................................................................92

5.2.1

Transaction Clock ........................................................................................................ 93

5.2.2

Programmable Range Chip Select .............................................................................. 93

5.2.3

LPC and FWH Address-to-X-Bus Address Translation ............................................... 93

5.2.4

Indirect Memory Read and Write Transactions ........................................................... 95

5.2.5

Mode 0, Normal Address X-Bus Transactions ............................................................ 95

5.2.6

Mode 0, Normal Address, Fast X-Bus Transactions ................................................... 97

5.2.7

Mode 0, Normal Address, Turbo X-Bus Transactions ................................................. 99

5.2.8

Mode 1, Normal Address Transactions ..................................................................... 100

5.2.9

Latched Address Mode X-Bus Transactions ............................................................. 101

5.3

X-BUS PROTECTION ............................................................................................................. 105

5.4

X-BUS REGISTERS ................................................................................................................ 107

5.4.1

X-Bus Register Map .................................................................................................. 107

5.4.2

X-Bus Configuration Register (XBCNF) .................................................................... 108

5.4.3

X-Bus Select Configuration Registers (XZCNF0 to XZCNF3) ................................... 108

5.4.4

X-Bus IRQ Configuration Register (XIRQC) .............................................................. 110

5.4.5

X-Bus Indirect Memory Address Register 0 (XIMA0) ................................................ 111

5.4.6

X-Bus Indirect Memory Address Register 1 (XIMA1) ................................................ 111

5.4.7

X-Bus Indirect Memory Address Register 2 (XIMA2) ................................................ 112

5.4.8

X-Bus Indirect Memory Address Register 3 (XIMA3) ................................................ 112

5.4.9

X-Bus Indirect Memory Data Register (XIMD) ........................................................... 112

5.4.10

X-Bus Select Mode Register (XZM0 to XZM3) .......................................................... 113

5.4.11

Host Access Protect Register (HAP0 to HAP1) ......................................................... 114

5.5

USAGE HINTS ........................................................................................................................ 115

5.6

X-BUS EXTENSION REGISTER BITMAP ............................................................................. 116

6.0

ACCESS.bus Interface

6.1

OVERVIEW ............................................................................................................................. 117

6.2

FUNCTIONAL DESCRIPTION ................................................................................................ 117

6.2.1

Bus Signals ................................................................................................................ 117

6.2.2

Data Transactions ..................................................................................................... 117

6.2.3

Start and Stop Conditions .......................................................................................... 118

6.2.4

Acknowledge (ACK) Cycle ........................................................................................ 118

6.2.5

Acknowledge after Every Byte Rule .......................................................................... 119

6.2.6

Addressing Transfer Formats .................................................................................... 119

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