PC87413 datasheet(62/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.9.3

Parallel Port Configuration Register

This register is reset by hardware to F2h.

Power Well:VDD

Location:Index F0h

Type:

R/W

Bit

76543210

Name

Parallel Port Mode Select

Extended

Access

Reserved

Power

Mode

Control

TRI-STATE

Control

Reset

11110010

Bit

Description

7-5

Parallel Port Mode Select.

000: SPP-Compatible mode. PD7-0 are always output signals

001: SPP Extended mode. PD7-0 direction is controlled by software

010: EPP 1.7 mode

011: EPP 1.9 mode

100: ECP mode (IEEE1284 register set), with no support for EPP mode

101: Reserved

110: Reserved

111: ECP mode (IEEE1284 register set), with EPP mode selectable as mode 4 (default)

Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2 conﬁguration register of the

parallel port at offset 02h.

Note: Before setting bits 7-5, enable the parallel port and set CTR/DCR (at base address + 2) to C4h.

Extended Register Access.

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are

ignored)

1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-

time configuration within the Parallel Port address space (default).

3-2

Reserved.

Power Mode Control. When the logical device is active:

0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.

Registers are maintained.

1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive (see Section 3.3.1 on page 43), the logical device

output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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