PC87413 datasheet(99/257 Pages) NSC

99 / 257 page

5.0 X-Bus Extension (Continued)

Revision 1.2

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5.2.7

Mode 0, Normal Address, Turbo X-Bus Transactions

The read and write transactions in Normal Address, Turbo X-Bus transactions provide a lower access time than those in

Mode 0, Normal Address, Fast X-Bus transactions. Because Normal Address, Turbo X-Bus transactions have seven fewer

cycles than Normal Address, Fast X-Bus transactions, they efficiently access very fast devices. This mode is selected for trans-

actions accessing XCSn by setting TRANSMD = 0 in the corresponding XZMn register and TBXCSn = 1 in the XBCNF register.

Read Transactions. When a read cycle on the LPC starts and the relevant XCSn is set to Turbo mode, a Mode 0, Normal

Address, Turbo X-Bus Transaction read cycle begins. A read cycle (Figure 21, below) starts by outputting the address on

address signals XA11-0 on the rising edge of the clock. During this time, the PC8741x device does not drive the data bus

signals XD7-0. One CLK cycle later, a chip-select signal XCSn is asserted. One CLK cycle after that, the XRD signal is as-

serted (set low), indicating a read cycle and enabling the accessed device to drive the data bus. In Turbo X-Bus transactions,

XRDY is ignored. Two CLK cycles later, the input data XD7-0 is sampled on the rising edge of the clock. One CLK cycle after

that, XRD is de-asserted (set high) and one CLK cycle later, the transaction is completed by de-asserting XCSn. The ad-

dress is retained for one more CLK cycle, after which the address lines are driven to 0.

Figure 19. Mode 0, Normal Address, Turbo X-Bus Transaction - Read Access Cycle

Write Transactions. When a write cycle on the LPC starts and the relevant XCSn is set to Turbo mode, a Mode 0, Normal

Address, Turbo X-Bus Transaction write cycle begins. A write cycle (Figure 22, below) starts by outputting the address on

address signals XA11-0 and the data signals on data pins XD7-0 on the rising edge of the clock. One CLK cycle later, a chip-

select signal XCSn is asserted. One CLK cycle after that, the XWR signal is asserted (set low), indicating a write cycle and

enabling the accessed device to be written. In Turbo X-Bus transactions, XRDY is ignored. Three CLK cycles later, XWR is

de-asserted (set high) and one CLK cycle after that, the transaction is completed by de-asserting XCSn and floating the data

bus signals XD7-0. One CLK cycle later, the address lines are driven to 0.

Figure 20. Mode 0, Normal Address, Turbo X-Bus Transaction - Write Access Cycle

CLK

(Internal; for

XD7-0

XA11-0

XCSn

XWR_XRW

XRD_XEN

XD7-0

(Data Read)

Reference Only)

CLK

(Internal; for

XD7-0

XA11-0

XCSn

XWR_XRW

XRD_XEN

Reference Only)

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