PC87413 datasheet(118/257 Pages) NSC

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6.0 ACCESS.bus Interface (Continued)

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Revision1.2

6.2.3

Start and Stop Conditions

The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus

remains busy until after a Stop Condition is generated. A high-to-low transition of the data line (ACBDAT) while the clock

(ACBCLK) is high indicates a Start Condition. A low-to-high transition of the ACBDAT line while the ACBCLK is high indi-

cates a Stop Condition (Figure 31).

A transaction begins with a Start Condition and ends with a Stop Condition. However, a Restart Condition can be generated

in the middle of a transaction (without the need for a Stop Condition) in order to change the direction of data transfer (from

address/data write to data read).

Before a Start condition, any changes of the ACBDAT line outside the high period of the ACBCLK are ignored. A Stop con-

dition encountered in mid-transaction on the ACBDAT line aborts the transaction. The PC8741x device releases the ACB-

DAT signal (to high level), thus generating Negative Acknowledge (NACK) cycles (see Section 6.2.4). In addition, the

PC8741x device sets the BUSERR bit in the ACBCST register (see Section 6.3.2 on page 127).

6.2.4

Acknowledge (ACK) Cycle

The ACK cycle involves two signals: the ACK clock pulse, sent by the master after each byte transferred, and the ACK data

signal, sent by the receiving device (see Figure 32).

The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter (master or slave)

releases the ACBDAT line (allows it to go high) to allow the receiver to send the ACK signal. The receiver must pull down

the ACBDAT line during the ACK clock pulse, signalling that it correctly received the previous data byte and is ready to re-

ceive the next byte. If the receiver does not pull the ACBDAT line (leaves it high), the transmitter identifies it as a NACK

condition (see Section 6.2.5). Figure 33 illustrates the ACK cycle.

ACBDAT

ACBCLK

S or R

Start or Restart

Condition

Stop

Condition

Figure 31. Start, Restart and Stop Conditions

Start

Condition

Stop

Condition

ACBDAT

ACBCLK

MSB

ACK

12 3 - 6

3 - 8

Acknowledge Signal

From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt is Serviced

Figure 32. ACCESS.bus Data Transaction with Acknowledge

LSB

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