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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87413 датащи(PDF) 209 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 209 Page - National Semiconductor (TI) |
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209 / 257 page  9.0 System Wake-Up Control (SWC) (Continued) Revision 1.2 209 www.national.com 9.4.8 General-Purpose Status 1 Register 0 (GPE1_STS_0) This register contains bits 0-7 of the GPE1_STS register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing ‘1’ to it) in the ACPI Specification. Power Well:VSB Location: Offset 00h Type: R/W1C 9.4.9 General-Purpose Status 1 Register 1 (GPE1_STS_1) This register contains bits 8-15 of the GPE1_STS register. This register belongs to the General-Purpose Event 1 Group of the ACPI fixed-feature space registers. The status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware signal and is only cleared by the software writing ‘1’ to it) in the ACPI Specification. Power Well:VSB Location: Offset 01h Type: R/W1C 4-2 R/W SLP_TYPx (Sleep Type). This field defines the system sleep state type (encoded). The states supported by the PC8741x devices are: Working (G0/S0), Sleeping (G1/S1-S4) and Soft-off (G2/S5). The encoding of the sleep state is programmed through the VPP-powered registers S0_SLP_TYP to S5_SLP_TYP. Bits 2 1 0 Function 0 0 0: Encoded 3-bit value for state Sn (n = 0-5); (default) x x x: Encoded 3-bit value (except 000b) for the remaining 5 sleep states: Sn (n = 0-5) 1- Ignored. The data written is ignored; the data read is undefined. 0- Reserved. Bit 76543210 Name GPIOE17 _STS GPIOE16 _STS GPIOE15 _STS GPIOE14 _STS GPIOE13 _STS GPIOE12 _STS GPIOE11 _STS GPIOE10 _STS Reset 00000000 Bit Description 7 GPIOE17_STS (GPIOE17 Event Status). Indicates that an active event has been detected at pin 7 of the GPIOE Port 1. The event has programmable polarity and the debounce option (see Section 7.3.1 on page 137). The bit is set by an active level at the GPIOE17 pin. Writing ‘1’ clears this bit; writing ‘0’ is ignored. 0: Inactive since last cleared (default) 1: An active event has occurred 6-0 GPIOE16_STS to GPIOE10_STS (GPIOE16 to GPIOE10 Event Status). Same as above for pins 6-0 of the GPIOE Port 1. Bit 76543210 Name GPIOE47 _STS GPIOE46 _STS GPIOE45 _STS GPIOE44 _STS GPIOE43 _STS GPIOE42 _STS GPIOE41 _STS GPIOE40 _STS Reset 00000000 Bit Type Description |
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