PC87413 datasheet(205/257 Pages) NSC

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9.0 System Wake-Up Control (SWC) (Continued)

Revision 1.2

205

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9.4.2

PM1 Status Low Register (PM1b_STS_LOW)

This register contains the eight low bits of the PM1_STS register. The PC8741x devices contain the block ‘b’ instance of the

PM1_STS register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers.

PM1_STS register bits that are specified by the ACPI but not implemented in the PC8741x devices have a ‘0’ value.

Power Well:VSB

Location: Offset 00h

Type:

9.4.3

PM1 Status High Register (PM1b_STS_HIGH)

This register contains the eight high bits of the PM1_STS register. The PC8741x devices contain the block ‘b’ instance of

the PM1_STS register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers.

PM1_STS register bits that are specified by the ACPI but not implemented in the PC8741x devices have a ‘0’ value. All the

implemented status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware

signal and is only cleared by the software writing ‘1’ to it) in the ACPI Specification.

Power Well:VSB

Location: Offset 01h

Type:

R/W1C

Bit

76543210

Name

Reserved

GBL_STS

BM_STS

Reserved

TMR_STS

Reset

00000000

Bit

Description

7-6

Reserved.

GBL_STS (Global Lock Status). Not implemented. Always at ‘0’.

BM_STS (Bus Master Status). Not implemented. Always at ‘0’.

3-1

Reserved.

TMR_STS (PM Timer Status). Not implemented. Always at ‘0’.

Bit

76543210

Name

WAK_STS

Reserved

Ignored

RTC_STS

SLPBTN

_STS

PWRBTN

_STS

Reset

00000000

Bit

Description

WAK_STS (Wake-up Event Status). Indicates that a power management event, enabled to generate SCI, has

occurred. This bit is set only if the system is in a sleep state (S1-S5). Writing ‘1’ while the system is in the

working state (S0), clears this bit; writing ‘0’ is ignored. When the system is in a sleep state (S1-S5) and an

enabled event is active, writing ‘1’ does not clear the WAK_STS bit.

0: Inactive (default)

1: At least one event enabled to SCI was active while the system was in a sleep state (S1-S5), since this bit was

last cleared

6-4

Reserved.

Ignored. The data written is ignored; the data read is undeﬁned.

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