PC87413 datasheet(212/257 Pages) NSC

212 / 257 page

9.0 System Wake-Up Control (SWC) (Continued)

www.national.com

212

Revision1.2

Bit

Description

SW_OFF_STS (Software Off Event Status). Indicates that the software wrote a ‘1’ to the SW_OFF_CTL bit in

the SWC_CTL register to request a VDD power off sequence. Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Inactive since last cleared (default)

1: ‘1’ was written to the SW_OFF_CTL bit in the SWC_CTL register

SW_ON_STS (Software On Event Status). Indicates that the software wrote a ‘1’ to the SW_ON_CTL bit in the

SWC_CTL register to request a VDD Power On sequence. When the VDD power is off, the SW_ON_CTL bit can

be written only through the ACCESS.bus (PC87413 and PC87417). Writing ‘1’ clears this bit; writing ‘0’ is

ignored.

0: Inactive since last cleared (default)

1: ‘1’ was written to the SW_ON_CTL bit in the SWC_CTL register

WDO_EVT_STS (Watchdog Event Status). Indicates that watchdog time-out has occurred. Writing ‘1’ clears

this bit; writing ‘0’ is ignored.

0: Inactive (default)

1: A watchdog time-out has occurred

MOD_IRQ_STS (Modules IRQ Event Status). Indicates that an IRQ was generated by one of the Legacy

modules (FDC, Parallel Port, Serial Port 1 and 2) or by the XIRQ pin (PC87416 and PC87417). For Legacy

modules IRQ, this bit is set only if the IRQ is enabled for wake-up (bit 4 of the Standard conﬁguration register

at index 70h) and the related module is active (see Section 3.2.3 on page 40). For the XIRQ pin, this bit is set

only if XIRQ is enabled for wake-up by setting both the IRQEN and the PWUREN bits in the XIRQC register

(see Section 5.4.4 on page 110) to ‘1’. Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Inactive since last cleared (default)

1: An enabled IRQ, from one of the Legacy modules or from the XIRQ pin, is active

MS_IRQ_STS (Mouse IRQ Event Status). Indicates that an IRQ was generated by the mouse interface section

of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Mouse Logical Device

conﬁguration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 40). Writing ‘1’

clears this bit; writing ‘0’ is ignored.

0: Inactive since last cleared (default)

1: An enabled IRQ, from the mouse interface section of the KBC module, is active

KBD_IRQ_STS (Keyboard IRQ Event Status). Indicates that an IRQ was generated by the keyboard interface

section of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Keyboard Logical

Device conﬁguration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 40). Writing

‘1’ clears this bit; writing ‘0’ is ignored.

0: Inactive since last cleared (default)

1: An enabled IRQ, from the keyboard interface section of the KBC module, is active

P12_EVT_STS (Port P12 Event Status). Indicates that an active high signal was generated by the KBC

module, at the P12 pin. This bit is set only if the KBC module is active (see Section 3.2.3 on page 40). Writing

‘1’ clears this bit; writing ‘0’ is ignored.

0: Inactive since last cleared (default)

1: An active high signal at the P12 pin was generated by the KBC module

RTC_EVT_STS (RTC Alarm Event Status). Indicates that an enabled RTC alarm has occurred. This bit is

similar to the RTC_STS bit in the PM1b_STS_HIGH register. Writing ‘1’ clears this bit and the RTC_STS bit in

the PM1b_STS_HIGH register; writing ‘0’ is ignored.

0: Inactive (default)

1: An RTC alarm has occurred

PC87413 датащи(PDF) 212 Page - National Semiconductor (TI)

PC87413 датащи(HTML) 212 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL