RM0319 datasheet(236/368 Pages) STMICROELECTRONICS

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I2C bus ports (I2C)

RM0319

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Doc ID 022640 Rev 3

RD_REQ

Read request.

This bit is set to ‘b1 when the I2C controller is acting as a slave and another

I2C master is attempting to read data from our module. The I2C controller

holds the I2C bus in waiting state (SCL tied to low) until this interrupt is

serviced. The processor must acknowledge this interrupt and then write

the request data to the IC_DATA_CMD register.

TX_EMPTY

Transmit buffer at threshold value.

This bit is set to ‘b1 when the transmit buffer is at or below the threshold

value set in the IC_TX_TL register. It is automatically cleared by hardware

when buffer level goes above the threshold.

TX_OVER

Transmit buffer filled to IC_TX_BUFFER_DEPTH.

This bit is set during transmit if the transmit buffer is filled to

IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C

command by writing to the IC_DATA_CMD register.

RX_FULL

Transmit buffer reach RX_TL threshold.

This bit is set when the transmit buffer reaches or goes above the threshold

set in the IC_RX_TL register. It is automatically cleared by hardware when

buffer level goes below the threshold.

RX_OVER

Receive buffer filled to IC_RX_BUFFER_DEPTH.

This bit is set when the receive buffer was completely filled to

IC_RX_BUFFER_DEPTH and more data arrived. The data is lost.

RX_UNDER

Receive buffer empty.

This bit is set when the processor attempts to read the receive buffer when

it is empty by reading from the IC_DATA_CMD register.

Table 67.

I2C controller interrupt sources (continued)

Name

Source

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