RM0319 datasheet(237/368 Pages) STMICROELECTRONICS

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RM0319

Synchronous serial ports (SSP)

Doc ID 022640 Rev 3

237/368

Synchronous serial ports (SSP)

This chapter focuses on SSP functionality and operation.

For technical details about the programmable registers related to the SSP, refer to the SSP

registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

18.1

Overview

The synchronous serial port (SSP) block includes a master or slave interface to enable

synchronous serial communication with slave or master peripherals.

18.2

Main features

●

Master or slave operation

●

Programmable clock bit rate and prescale

●

Separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations

deep

●

Programmable choice of interface operation, SPI, Microwire, or TI synchronous serial

●

Programmable data frame size from 4 to 16 bits

●

Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts

●

Internal loopback test mode available

●

Support for direct memory access (DMA)

18.3

Pins

Table 68.

SSP pin description

SSP Port

SSP in master mode

SSP in slave mode

Function

Direction

Function

Direction

SSP0_MOSI

Transmit Data

Out

Receive Data

SSP0_MISO

Receive Data

Transmit Data

Out

SSP0_CLK

Clock

Out

Clock

SSP0_SS0

Slave select (chip-select)

Out

Slave select (chip-select)

SSP0_CS2

Slave select (chip-select)

Out

Not Used

SSP0_CS3

Slave select (chip-select)

Out

Not Used

SSP0_CS4

Slave select (chip-select)

Out

Not Used

SSP1_MOSI

Transmit Data

Out

Receive Data

SSP1_MISO

Receive Data

Transmit Data

Out

SSP1_CLK

Clock

Out

Clock

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