RM0319 datasheet(239/368 Pages) STMICROELECTRONICS

239 / 368 page

RM0319

Synchronous serial ports (SSP)

Doc ID 022640 Rev 3

239/368

18.4.3

Clock prescaler

When configured as a master, an internal prescaler, comprising two free-running re-

loadable serially linked counters, is used to provide the serial output clock SSPx_CLK (x is

either 0, 1 or 2).

You can program the clock prescaler, through the SSPCPSR register, to divide input clock

(PCLK, which is internal to the device) by a factor of 2 to 254 in steps of two. By not utilizing

the least significant bit of the SSPCPSR register, division by an odd number is not possible

and this ensures a symmetrical (equal mark space ratio) clock is generated.

The output of the prescaler is further divided by a factor of 1 to 256, through the

programming of the SSPCR0 control register, to give the final master output clock

SSPx_CLK.

18.4.4

Transmit FIFO

The common transmit FIFO is a 16-bit wide, 8-location deep, first-in, first-out memory buffer.

CPU data written across the AMBA APB interface are stored in the buffer until read out by

the transmit logic.

When configured as a master or a slave parallel data is written into the transmit FIFO prior

to serial conversion and transmission to the attached slave or master respectively, through

the SSPx_MOSI or SSPx_MISO pin (based on the master or slave mode of operation

respectively).

18.4.5

Receive FIFO

The common receive FIFO is a 16-bit wide, 8-location deep, first-in, first-out memory buffer.

Received data from the serial interface are stored in the buffer until read out by the CPU

across the AMBA APB interface.

When configured as a master or slave, serial data received through the SSPx_MISO or

SSPx_MOSI pin (based on the master or slave mode of operation respectively) is registered

prior to parallel loading into the attached slave or master receive FIFO respectively.

18.4.6

Transmit and receive logic

When configured as a master, the clock to the attached slaves is derived from a divided

down version of PCLK through the prescaler operations described previously. The master

transmit logic successively reads a value from its transmit FIFO and performs parallel to

serial conversion on it. Then the serial data stream and frame control signal, synchronized

to SSPx_CLK, are output through the SSPx_MOSI pin to the attached slaves. The master

receive logic performs serial to parallel conversion on the incoming synchronous

SSPx_MISO data stream, extracting and storing values into its receive FIFO, for subsequent

reading through the APB interface.

When configured as a slave, the SSPx_CLK clock is provided by an attached master and

used to time its transmission and reception sequences. The slave transmit logic, under

control of the master clock, successively reads a value from its transmit FIFO, performs

parallel to serial conversion, then output the serial data stream and frame control signal

through the slave SSPx_MISO pin. The slave receive logic performs serial to parallel

conversion on the incoming SSPx_MOSI data stream, extracting and storing values into its

receive FIFO, for subsequent reading through the APB interface.

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