RM0319 datasheet(80/368 Pages) STMICROELECTRONICS

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Multiport DDR controller (MPMC)

RM0319

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Doc ID 022640 Rev 3

designated to any available buffer. However, back-to-back write requests from a particular

source ID will be allocated to the same WRITE buffer as the previous command.

Since the core must pull data out of the buffers in the order it was stored, if a WRITE

command is linked to a buffer associated with another command in the queue, the new

command will be placed in the command queue after that command, regardless of priority.

This feature is always enabled.

●

Priority

Priorities are used to distinguish important commands from less important commands. Each

command is given a priority based on the command type through the programmable

parameters ahbX_r_priority and ahbX_w_priority (X is the x-th port), where '0' value is the

highest priority and '7' is the lowest.

The placement algorithm will attempt to place higher priority commands ahead lower priority

commands, as long as they have no source ID, WRITE buffer or address collisions.

Higher priority commands will be placed lower in the command queue in case:

●

They access the same address and

●

They are from the same requestor or

●

They use the same buffer used by lower priority commands being in the command

queue already.

This feature is enabled through the priorities parameter.

●

Bank splitting

Before accesses to two different rows within the same bank could be performed, first active

row must be closed (pre-charged) and the new row must be opened (activated). Therefore,

the both activities require some timing overhead for optimization, the placement queue will

attempt to insert the new command into the command queue such that commands to other

banks may execute during this timing overhead.

Still the placement of the new commands will follow priority, source ID, WRITE buffer and

address collision rules. The placement logic will also attempt to optimize the core, by

inserting a command to the same bank of any existing command in the command queue,

immediately after the original command. This reduces the overall timing overhead by

potentially eliminating one pre-charge/activate cycle. This placement will only be possible if

there are no priority, source ID, WRITE buffer or address collisions or conflicts with other

commands in the command queue.

Every bank splitting feature could be enabled through the bank_split_en parameter.

●

Read/Write grouping

The memory suffers a small timing overhead when switching from READ to WRITE mode.

For efficiency, the placement queue will attempt to place a new read command sequentially

with other read commands in the command queue, or a new WRITE command sequentially

with other WRITE commands in the command queue. Grouping will only be possible if no

priority, source ID, WRITE buffer or address collision rules are violated.

This feature is enabled through the rw_same_en parameter.

Command execution order after placement

Once a command has been placed in the command queue, its order relative to the other

commands in the queue at that time is fixed. Even if this simplifies the algorithm there are

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