 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
RM0319 датащи(PDF) 240 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
RM0319 датащи(HTML) 240 Page - STMicroelectronics |
|
|
240 / 368 page  Synchronous serial ports (SSP) RM0319 240/368 Doc ID 022640 Rev 3 18.4.7 DMA interface This block manages the DMA interface. It can work in single transfer mode or in burst transfer mode. Refer to the Chapter 36: DMA controller (DMAC) for more details on this interface. 18.4.8 Interrupt generation The SSP generates four individual maskable, active HIGH interrupts. A combined interrupt output is also generated as an OR function of the individual interrupt requests. You can use the single combined interrupt with a system interrupt controller that provides another level of masking on a per-peripheral basis. This allows use of modular device drivers that always know where to find the interrupt source control register bits. The individual interrupt requests could also be used with a system interrupt controller that provides masking for the outputs of each peripheral. In this way, a global interrupt controller service routine would be able to read the entire set of sources from one wide register in the system interrupt controller. This is attractive where the time to read from the peripheral registers is significant compared to the CPU clock speed in a real-time system. The peripheral supports both the above methods. The transmit and receive dynamic data-flow interrupts are separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. See also: Section 18.6: Interrupts. 18.5 Operation 18.5.1 Configuring the SSP After reset, the SSP logic is disabled and must be configured. The control registers SSPCR0 and SSPCR1 need to be programmed to configure the peripheral as a master or slave operating under one of the following protocols: ● Motorola SPI ● Texas Instruments SSI ● National Semiconductor The bit rate, derived from the APB clock (PCLK), requires the programming of the clock prescale register SSPCPSR. (Refer to the miscellaneous registers description for the PCLK frequency). Chip select for SSP0 - only in master mode of operation In the master mode of operation, SSP0 can select between four slaves connected externally. This is achieved through a separate chip select (CS) generation logic using the basGPIO module. GPIODATA[7] and [6] are used to route the single CS generated by the SSP0 block to four external pins. The external CS is generated as per the following table: |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
