RM0319 datasheet(234/368 Pages) STMICROELECTRONICS

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I2C bus ports (I2C)

RM0319

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Doc ID 022640 Rev 3

17.5

Clocks

All masters generate their own clock to transfer messages, and data is valid only during the

high period of SCL clock.

Clock synchronization is performed using the wired-AND connection to the SCL signal.

When the master transitions the SCL clock to ‘b0, the master starts counting the low time of

the SCL clock and transitions the SCL clock signal to ‘b1 at the beginning of the next clock

period. However, if another master is holding the SCL line to ‘b0, then the master goes into

a high wait state until the SCL clock line transitions to ‘b1.

All masters then count off their high time, and the master with the shortest high time

transitions the SCL line to ‘b0. The masters counts out their low time and the one with the

longest low time forces the other master into a high wait state. Therefore, a synchronized

SCL clock is generated.

Note:

Optionally, slaves may hold the SCL line low to slow down the timing on the I2C bus.

Figure 85.

Clock synchronization

17.6

Interrupts

The following table lists the interrupt generated within the I2C controller. These interrupt

sources could be masked using the IC_INTR_MASK register.

Interrupts status (after masking) and raw interrupts status (before masking) are available

through IC_INTR_STAT and IC_RAW_INTR_STAT register, respectively.

CLKA

CLKB

SCL

Wait

State

Start counting HIGH

period

SCL LOW Transition Resets all CLKs

to start

counting their LOW periods

SCL Transitions HIGH

when all CLKs are in HIGH state

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