RM0319 datasheet(91/368 Pages) STMICROELECTRONICS

91 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

91/368

The delay compensation circuitry relies on a master/slave approach. There is a master

delay line which is used to determine how many delay elements constitute a complete cycle.

This count is used, along with the programmable fractional delay settings, to determine the

actual number of delay elements to program into the slave delay lines. The master and slave

delay lines are identical. This approach allows the memory controller to observe a clock and

then delay other signals a fixed percentage of that clock. The DCC logic does not actively

generate clock signals.

The delay parameters are listed in Table 33. The total delay can be determined based on

the following equation, where param is one of the parameters in the table:

delay = #delays in one cycle × (param[6:0]) /128

Separate delay chains for each DQS signal from the DRAM devices.

Support for multiple DQ:DQS ratios

The DQS bus is a bidirectional bus that is driven by the memory controller on writes and the

memory on reads. When neither device is driving the bus, DQS will remain in a high-

impedance state. However, DQS is only relevant to the memory controller during reads in

order to capture valid data. For this reason, the DQS signal from memory must be gated so

that it is ignored at all other times. Gating of the DQS signal is shown in Figure 4, DQS

gating.

The timing of when to start gating the DQS depends on the design itself, the flight time of

the clock to memory, and the flight time of the data/DQS to the memory controller, as

follows:

●

If the round trip time is between ½ cycle and 1½ cycles, program the caslat_lin

parameter equal to the caslat parameter.

●

If the round trip time is less than ½ cycle, program the caslat_lin parameter one value

less (which translates to ½ cycle) than the caslat parameter to open the gate ½ cycle

sooner.

●

lf the round trip time is longer than 1½ cycles, program the caslat_lin parameter one

value more (which translates to ½ cycle) than the caslat parameter to open the gate ½

cycle later.

In addition, the caslat_lin_gate parameter controls the opening of the gating signal.

Nominally, caslat_lin_gate should have the same value as the caslat_lin parameter.

However, to accommodate the skew of the memory devices, it may be necessary to open

the gate a 1/2-cycle sooner or later. Adjusting the value of caslat_lin_gate modifies the gate

opening by this factor.

6.5

Reset

There are two sets of reset logic inside the memory controller: the reset for the memory

controller core and the reset for the AHB ports.

Table 33.

Delay parameters

Operation

Parameter

Clock

wr_dqs_shift

Read

dll_dqs_delay_X

Write

dqs_out_shift

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