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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0319 датащи(PDF) 56 Page - STMicroelectronics |
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RM0319 датащи(HTML) 56 Page - STMicroelectronics |
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56 / 368 page  Multiport DDR controller (MPMC) RM0319 56/368 Doc ID 022640 Rev 3 ● Configurable memory parameters: – Row address from 8 to 15 bits – Column address from 7 to 14 bits – Memory internal banks 4 or 8 ● Programmable DQS0/1 signals per byte configurable single ended and differential mode ● Built-in adjustable delay compensation circuitry (DCC) for reliable data sends and captures timing ● Dynamic memory self refresh power reduction automatically activated from SoC power management unit 6.3 Functional description Figure 15. MPMC block diagram The multiport memory controller supports high memory bandwidth and an efficient arbitration scheme for high priority agent requests. The memory controller architecture consists of the following main sub-blocks: ● AHB port interfaces ● Arbiter ● Command queue with placement logic ● Write data queue ● DRAM command processing The core controller interfaces with standard AHB ports through the interface blocks. All requests are processed through the internal arbiter which feeds single commands to the command queue of the core controller. Write and read data is routed independently of the arbiter through the data interfaces. There are multiple write data interfaces to the write data AHB-CFG AHB0 AHB1 AHB2 AHB3 AHB4 PHY Ext.Memory I/F Multi port Memory Controller CORE Controller |
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