RM0319 datasheet(60/368 Pages) STMICROELECTRONICS

60 / 368 page

Multiport DDR controller (MPMC)

RM0319

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Doc ID 022640 Rev 3

6.3.2

AHB register port

The AHB memory controller interface contains a special register port for converting AHB

However, unlike the data ports, the register port has no allocated storage in the form of

FIFOs.

The register port only supports the AHB SINGLE transaction burst types for all transactions

with a bytes-per-beat (2ahbX_HSIZE) equal to or less than the width of the AHB register

bus. There is no support for WRAP transactions or early burst termination for the register

port. BUSY cycles can be inserted between the incrementing burst operations.

Similar to the data ports, the AHB register port responds to illegal conditions with the

ERROR response. However, a register port ERROR will only occur when the transaction

address is not aligned to the size of the transaction.

All parameters related to the AHB port operation are located in the MPMC core register

map.

These parameters are programmed during the MPMC initialization sequence along with all

of the other device parameters. A typical boot-up sequence includes a reset of the AHB

ports as well as of the MPMC core, followed by core setting for AHB operation by AHB

6.3.3

AHB transactions

The AHB memory controller supports the complete set of AHB transactions. The list

includes: SINGLE, INCR4, INCR8, INCR16, WRAP4, WRAP8, WRAP16 and INCR.

For documentation purposes, INCRx will refer to INCR4, INCR8 or INCR16 commands.

WRAPx will refer to WRAP4, WRAP8 or WRAP16 commands. Command handling is

defined for full-size transfers, in which the bytes-per-beat is equal to the bus width, or narrow

transfers, where the bytes-per-beat is less than the bus width.

Full-Size SINGLE, INCRx or WRAPx transactions

SINGLE and INCRx transactions with a bytes-per-beat value (2ahbX_HSIZE) equal to the

width of the AHB bus are issued as single memory controller commands to the core. The

starting address of the transaction is the same as the address specified during the first

NONSEQ beat of the corresponding AHB transaction. The MPMC core accepts these

commands in a pipelined fashion such that, for read transactions, the READ data can be

delivered in contiguous data words back to the AHB interface. These words may not be

contiguous if other AHB requests with higher priority get placed ahead of some of these

commands, or if the read queue inside the core is not deep enough to absorb a full burst.

Table 15.

Configured AHB settings

Port

number

Data

width

Clock domain type

Command

FIFO depth

Write FIFO

depth

Read FIFO

depth

Async or Sync

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