RM0319 datasheet(84/368 Pages) STMICROELECTRONICS

84 / 368 page

Multiport DDR controller (MPMC)

RM0319

84/368

Doc ID 022640 Rev 3

Manual “On-Demand” entry

Manual Entry occurs when the 2 following conditions are matched:

●

The mode is programmed for manual entry by clearing the relevant bit in the

lowpower_auto_enable parameter to 1'b0.

●

The particular mode is set to 1'b1 in the lowpower_control parameter.

For manual entry, the lowpower_control parameter triggers the entry into the low power

modes. The MPMC does not need to be idle when the low power mode bit is enabled. When

a particular mode that is programmed for manual entry is enabled, the MPMC will complete

the current memory burst access, and then, regardless of the activity inside the MPMC or at

the memory interface, it will enter the selected low power mode.

If any new transaction would involve the MPMC while it is in any of the low power modes, the

transaction itself will be stacked inside the MPMC's command queue until the queue is

completely full.

The way to exit from a manually-entered low power mode is manual too. Clearing the

lowpower_control parameter bits to 1'b0 will trigger the memory controller to pull the

memory devices out of powerdown or self-refresh, and command processing will resume.

Note:

In the deepest low power mode (Mode 5), the clock toward the programming registers

module is gated off. However, manual low power mode exit requires the user to clear the

lowpower_control parameter to 1'b0, which is not possible when the clock is off. As a result,

the user should not manually activate the deepest low power mode. If Memory Self-Refresh

with Memory and Controller Clock Gating Mode (Mode 5) was entered manually, the device

would not be able to be brought out of low power mode again.

If a different lowpower_control bit is set to 1'b1 while in one of the low power modes, or on

clearing of the original bit to 1'b0, the memory controller will exit the current low power

mode. There will be at least a 15 cycle delay before the component being either fully

operational or enters the new low power mode.

6.4.3

Low power control programming

The low power modes of the memory controller are controlled by the lowpower_control and

lowpower_auto_enable parameters. These 5-bit parameters contain each one bit to control

each low power mode. The lowpower_control parameter enables the associated low power

mode, and the lowpower_auto_enable parameter sets the entry method into that mode as

manual or automatic. Table 30 displays the relationship between the 5 bits of the

lowpower_control and lowpower_auto_enable parameters and the various low power

modes.

Table 30.

Low power mode parameters

Low Power Mode

Enable

Entry

Memory Power-Down (Mode 1)

lowpower_control [4] =1'b1

lowpower_auto_enable [4]:

1'b0 = Manual

1'b1 = Automatic

Memory Power-Down with Memory

Clock Gating (Mode 2)

lowpower_control [3] =1'b1

lowpower_auto_enable [3]:

1'b0 = Manual

1'b1 = Automatic

RM0319 датащи(PDF) 84 Page - STMicroelectronics

RM0319 датащи(HTML) 84 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL