RM0319 datasheet(233/368 Pages) STMICROELECTRONICS

233 / 368 page

RM0319

I2C bus ports (I2C)

Doc ID 022640 Rev 3

233/368

Master transmit and master receive

The I2C controller supports switching back and forward between reading and writing

dynamically. To transmit data, write the data to be written to the lower byte of the

IC_DATA_CMD register. The CMD bit in the same register should be written to ‘b0 meaning

a write operation. Subsequently, a read command may be issued by writing “don’t care” to

the lower byte of the IC_DATA_CMD register, and a ‘b1 should be written to the CMD bit.

As data is transmitted and received, transmit and receive buffer status bits and interrupts

change accordingly.

17.4.3

Multimaster mode

In a multiple master I2C bus system, the I2C controller should not be programmed as a

master device. For multiple master systems, the I2C controller can only be operated as a

slave (set IC_CON.MASTER_MODE to 0 (master disabled).

The I2C controller bus protocol allows multiple masters to reside on the same bus. When

two or more masters try to transfer information on the bus at the same time, they must

arbitrate and synchronize the SCL clock.

Master arbitration

Arbitration takes place on the SDA line, while the SCL line is ‘b1. The master, which

transmits a ‘b1 while the other master transmits ‘b0, loses arbitration and turns off its data

output. The master that lost arbitration can continue to generate clocks until the end of the

byte transfer. If both masters are addressing the same slave device, the arbitration could go

into the data phase.

For high-speed mode, the arbitration can not go into the data phase, because each master

is programmed with a different high-speed master code. Because the codes are unique,

only one master can win arbitration, which occurs by the end of the transmission of the high-

speed master code.

Figure 84.

Multiple master arbitration

DATA2

DATA1

SDA

SCL

MSB

matching data

‘1’

‘0’

DATA1 loses arbitration

SDA mirrors DATA2

SDA lines up with

DATA1 START

condition

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