RM0319 datasheet(82/368 Pages) STMICROELECTRONICS

82 / 368 page

Multiport DDR controller (MPMC)

RM0319

82/368

Doc ID 022640 Rev 3

6.4

Operation

In many applications, it is highly desirable to minimize power consumption. The MPMC

provides various user configurable low power options to manage power savings. In addition,

a partial-array self-refresh option is included for mobile memory devices.

6.4.1

Low power modes

Five low power modes are available in the memory controller. The low power modes are

listed from least to most power saving.

Note:

It is not possible to exit one low power mode and enter another low power mode

simultaneously. The user should plan for a minimum delay between exit and entry between

the two low power modes of 15 cycles in which the MPMC must remain stable.

Memory Power-Down

The memory controller sets the memory devices into power-down which reduces the

overall power consumption of the system. This is the low power modes having the least

effect: The memory controller and memory clocks are fully operational, but the CKE

input bit toward the memory devices is de-asserted.

The memory controller will continue to monitor memory refresh needs and will

automatically bring the memory out of power-down to perform these refreshes.

Whenever a refresh is required, the CKE bit will be turned enabled. This action drives

memory devices out power-down. Once the refresh has been completed, the memory

devices will be returned to power-down by de-asserting the CKE input bit.

Memory Power-Down with Memory Clock Gating

The memory controller sets the memory devices into power-down and gates off the

clock to the memory devices. Refresh operations will be handled as seen above for the

Memory Power-Down mode (Mode 1), but the gating on the memory clock will be now

removed before asserting the CKE pin. After the refresh has been completed, the

memory devices will be returned to power-down with the clock gated. Before the

memory devices are removed from power-down, the clock will be gated on again.

Although this mode is supported in both mobile and non-mobile memory devices, clock

gating while in power-down is only allowed for mobile memory devices. Therefore, the

MPMC will only attempt to gate the clock if it is configured for mobile device operation.

For non-mobile memory devices in this low power mode, the MPMC will operate

identically to the Memory Power-Down mode without the clock gating (Mode 1).

Memory Self-Refresh

The MPMC sets the memory devices into self-refresh. In this mode, the MPMC and

memory clocks are fully operational and the CKE input bit to the memory devices is de-

asserted. Since the memory automatically refreshes its contents, the MPMC does not

need to send explicit refreshes to the memory.

Memory Self-Refresh with Memory Clock Gating

The MPMC sets the memory devices into self-refresh and gates off the clock to the

memory devices. Before the memory devices are removed from self-refresh, the clock

will be gated on again.

Memory Self-Refresh with Memory and Controller Clock Gating

This is the most effective low power mode of the memory controller: The memory

controller sets the memory devices self-refreshing and gates off the clock toward them.

In addition, the clock toward the MPMC and the programming parameters will be gated

off, except to a small portion of the DLL, which must remain active to maintain the lock.

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