RM0319 datasheet(79/368 Pages) STMICROELECTRONICS

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RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

79/368

maximize efficiency of the core through command grouping and bank splitting. Once placed

into the command queue, the relative order of commands is constant.

Many of the rules used in placement may be individually enabled/disabled. In addition, the

queue may be programmed by the placement_en parameter to disable the placement logic

entirely, resulting in an in-line queue that attends requests in the order they are received. If

the placement_en parameter is cleared to 1'b0, the placement algorithm will be ignored.

Rules of the placement algorithm

The factors affecting command placement together work to identify where a new command

fits into the execution order. They are listed in order of importance.

●

Address collision/Data coherency violation

The order in which READ and WRITE commands are processed inside MPMC is critical to

proper system behavior. While READs and WRITEs to different addresses are independent

and may be re-ordered without affecting system performance, READs and WRITEs that

access the same address are significantly related. If the port requests a READ after a

WRITE to the same address, then repositioning the READ before the WRITE would return

the original data, not the changed data. Similarly, if the READ was requested ahead of the

WRITE but accidentally positioned after the WRITE, the READ would return the new data,

not the original data prior to being overwritten. These are significant data coherency

mistakes.

To avoid address collisions, READs or WRITEs that access the same chip select, bank and

row as a command already in the command queue will be inserted into the command queue

after the original command, even if the new command is of a higher priority.

This factor may be enabled/disabled through the addr_cmp_en parameter and should only

be disabled if the system can guarantee coherency of READs and WRITEs.

●

Source ID collision

Each port is assigned a specific source ID that identifies the source uniquely. This allows the

memory controller to map data from/to the correct source/destination.

Note:

A source ID does contain port identification information which means that the rules for

placement are dependent on the requesting port. There will not be source ID collisions

between ports.

In general, commands of the same type from the same source ID will be placed in the

command queue in order. Therefore, a READ/WRITE command with the same source ID of

a READ/WRITE command being already in the command queue will be processed

afterward.

The behavior of commands of different types from the same source ID is dependent on the

user configuration. For MPMC, the placement of new READ/WRITE commands that collide

in terms of source ID with existing entries in the command queue will only depend on other

commands of the same type, not on different types. This means that, if there are no address

conflicts, a READ command could be executed ahead of a WRITE command with the same

source ID, as a WRITE command could be executed ahead of a READ command with the

same source ID as well.

This feature is always enabled.

●

Write buffer collision

Incoming WRITE requests in the command queue are allocated to one of the 8 WRITE

buffers of the core automatically based on availability. New WRITE commands will be

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