RM0319 datasheet(232/368 Pages) STMICROELECTRONICS

232 / 368 page

I2C bus ports (I2C)

RM0319

232/368

Doc ID 022640 Rev 3

If the remote master is to receive n bytes from the I2C controller, but a number of bytes

larger than n is written to the Transmit FIFO then, when the slave finishes sending the

requested n bytes, it will clear the Transmit FIFO and ignore any excess bytes.

17.4.2

Master mode

Initial configuration

To use the I2C controller as a master, you must perform the following steps:

Disable the I2C controller by writing a 1‘b0 to the IC_ENABLE register.

Write to the IC_CON register to set the maximum speed mode supported and the

desired speed of the I2C controller master-initiated transfers, 7- or 1-0 bit addressing.

Write to the IC_TAR register the address of the I2C device to be addressed by the I2C

controller as a master (10-bit field IC_TAR). It also indicates whether adding a START

BYTE or issuing a general call is going to occur (through the GC_OR_START bit on the

same register), The desired speed of the I2C controller master-initiated transfer is

controlled by the IC_10BITADDR_MASTER bit in the IC_TAR register,

For high-speed mode transfer only: the desired master code for I2C controller must be

written to the IC_HS_MADDR register (3-bit IC_HS_MAR field),

Enable again the I2C controller setting the IC_ENABLE register,

Command and data to be sent may be written now to the IC_DATA_CMD register. If this

the buffers are kept cleared when I2C controller is not enabled.

Dynamic IC_TAR or IC_10BITADDR_MASTER update

The I2C controller supports a dynamic IC_TAR or IC_10BITADDR_MASTER update.

Even if the slave part of the DW_apb_i2c is involved in an I2C transfer, both of the following

must occur:

●

MST_ACTIVITY must be IDLE, that is, IC_STATUS[5] = ‘b0,

●

Transmit FIFO completely empty must occurs, that is, IC_STATUS[2] = ‘b0.

Note:

If a bulk read is performed on the slave part of the DW_apb_i2c over the I2C bus, then only

MST_ACTIVITY must be IDLE, that is, the Transmit FIFO does not need to be completely

empty. This is a very specific case and should be monitored in software.

To write to the IC_TAR register, dynamically write the IC_TAR and

IC_10BITADDR_MASTER using the following requirements:

●

IC_TAR[12] = IC_10BITADDR_MASTER. Master uses 7 or 10 bit addressing and is

writable when the conditions in step 1 are met and if I2C_DYNAMIC_TAR_UPDATE is

set to ‘b1,

●

IC_TAR[11:10] = Only writable when DW_apb_i2c interface is disabled, which

corresponds to the IC_ENABLE register being set to ‘b0. otherwise writes have no

effects,

●

IC_TAR[9:0] = IC_TAR. Master’s 10 bit target address is writable at any time when the

conditions in step 1 are met and if I2C_DYNAMIC_TAR_UPDATE is set to ‘b1.

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