RM0319 datasheet(62/368 Pages) STMICROELECTRONICS

62 / 368 page

Multiport DDR controller (MPMC)

RM0319

62/368

Doc ID 022640 Rev 3

too high, then write transactions may force the AHB port to issue masked WRITE

commands (WRITE commands that do not alter the contents of memory) to the core to

complete the transactions. Similarly, for READ transactions, programming the length too

large will cause extraneous data to be gathered, wasting cycles. An optimal value for the

READ and WRITE length is important.

Note:

The values in the ahbX_wrcnt and ahbX_rdcnt parameters should never exceed 1024.

The first command is issued when the AHB request is decoded. Subsequent read

commands are issued when the last word of data has been delivered from the core to the

AHB port.

Subsequent WRITE commands are issued after the last WRITE data word of the last

command has been transferred from the AHB bus to the core.

Narrow SINGLE or INCRx transactions

For INCRx transactions with a bytes-per-beat less than the width of the AHB data bus, the

port gathers data from the AHB master until it collects all the data needed to form a

complete data word, or until the completion of the transaction.

The data is then issued to the core as multiples of the complete data word. If the start or end

of a WRITE transaction is not aligned to the data word boundary, the appropriate bytes are

masked off when the data is sent to the core. This provides a significant optimization in the

port, preventing the core's Write Data Queue from filling with a large number of small data

chunks. Performance is also improved significantly by allowing the core to write a complete

word of data in a single burst instead of small sections of the word in several bursts. The

reverse operation is done for INCRx READ transactions. The AHB port issues a READ of

the complete word and then divides the READ data into smaller components depending on

the size specified with the READ request. The alignment of data bytes within the AHB bus

for transaction with a size less than the bus data width depends on the address of the

written or read bytes. The AHB master is responsible for aligning the WRITE data bytes in

the appropriate byte lanes of the AHB bus for these transactions. Similarly, the AHB master

should mask out any data that is not in the appropriate byte lanes for the READ transaction

as don't-care bytes.

Narrow WRAPx or INCR transactions

This optimization is NOT performed for WRAPx transactions with a bytes-per-beat less than

width or INCR transactions of unspecified lengths. Each beat of these kinds of transactions

is issued to the core as a separate transaction, thereby occupying a separate queue entry.

Therefore, these transactions are inefficient and should only be used if necessary.

Data Alignment for Narrow transactions

Examples of the alignment of READ/WRITE data for a 64 bit wide AHB bus with BYTE,

HALFWORD and WORD transactions at different addresses is shown in Table 16 and

Table 17.

Table 16.

READ/WRITE data alignment - Little Endian

Transaction type

Address

Data alignment - little endian

BYTE

0x0

0x--------------Aa

BYTE

0x1

0x------------Aa--

BYTE

0x2

0x----------Aa----

BYTE

0x3

0x--------Aa------

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