RM0319 datasheet(88/368 Pages) STMICROELECTRONICS

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Multiport DDR controller (MPMC)

RM0319

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Doc ID 022640 Rev 3

6.4.8

Half datapath option

The memory controller can also reduce the usable size of the bus between the memory

controller itself and memory devices. This feature is very useful when a different memory

part, having a smaller data width, is utilized. To use a memory device with a smaller

datapath, the half datapath option could be enabled setting the programmable reduc

parameter to 1'b1. The memory interface consists of the data signal (DQ) [15:0], data strobe

(DQS) [1:0] and data mask (DM) [1:0]. When the reduc parameter is set to 1'b1, only the

lower half of the memory interface is used. In this setting, the upper half bits of the

dm_disable, dqs_disable and data_disable signals are driven high, causing the upper half of

the data and data strobe buses to be driven low. The upper half of the data mask bus is

driven high.

If the reduc parameter is cleared to 1'b0, the memory controller will ignore the half datapath

option and work normally. In this case, the entire memory interface will be used. Table 32

displays the effect of the Half Datapath option on the memory interface buses.

6.4.9

User-defined registers

The memory controller contains two user-defined parameters. These register-width size

parameters hold user-defined values that will be available as output signals

param_user_def_reg_X (X is 0 or 1) at the core (stp_memcd) level. These parameters have

no effect on the memory controller except that utilizing addresses in the register map.

Only a single bit of the user-defined registers is used in this configuration. All other bits of

user_def_reg_0 and user_def_reg_1 are available if customer hookup is required.

Bit 0 of user_def_reg_0 controls the READ data retime function. This function provides the

user with a choice in clock synchronization paths in the PHY.

An alternative path has been created allowing the PHY to synchronize the READ data to the

core clock domain and then pass the data to the read FIFO synchronously, i.e. in 1one clock

cycle. This constrains the 1/4 cycle path for clock synchronization within the PHY between

two flip-flops which are easily co-located, however it adds a cycle of latency to the path.

Bit 0 of user_def_reg_0 allows the user to select the desired path. If the bit is cleared to

1'b0, the alternative path is used and synchronization occurs in the PHY, incurring the extra

cycle of latency. If the bit is set to 1'b1, the standard path is used.

6.4.10

Address mapping

The memory controller automatically maps user addresses to the DRAM memory in a

contiguous block. Address map begins at user address 0 and finishes at the highest

available address according to the size and number of DRAM devices present. This

mapping is dependent on how the memory controller is configured and how the parameters

Table 32.

Memory interface buses with Half Datapath option

Signal

Reduc parameter is set (1‘b1)

Reduc parameter is cleared(1‘b0)

Bus size

Relevant bit

Bus size

Relevant bit

Data DQ

[15:00]

[07:00]

[15:00]

Data DQS

[01:00]

[00:00]

[01:00]

Data DM

[01:00]

[00:00]

[01:00]

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