RM0319 datasheet(65/368 Pages) STMICROELECTRONICS

65 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

65/368

transaction of the length specified to the core. The length is a defined quantity that is

specified at the beginning of the transaction. For WRITE transactions, the AHB port

forwards the data from the AHBx HWDATA signals provided by the AHB master to the core.

If the WRITE transaction is early burst-terminated, the port will continue the data stream, but

issue masked WRITE data for the duration of the transaction instead. This allows the whole

transaction to be completed without corrupting data in memory.

For READ transactions, the AHB port returns the expected number of bytes of data to the

AHB master. If a READ transaction is early burst-terminated, the MPMC continues to send

the READ data from the core, but the data is not forwarded back to the AHB master.

Errors

●

Error types

When an illegal operational condition is detected on a new AHB transaction entering the

port (i.e. during a NONSEQ burst), the port responds with an ERROR. The ERROR is a two-

cycle response as dictated by the AHB protocol. In the first cycle, the ahbX_HREADY signal

is low and in the second cycle, the ahbX_HREADY signal is high. The illegal conditions

which generate this error are:

Transactions with a bytes-per-beat greater than the width of the AHB bus.

The transaction address is not aligned to the size of the transaction. This is a

requirement of the AHB protocol.

●

Error handling

Once a port error is detected in the MPMC core, the following actions occur:

The internal interrupt signal controller_int is asserted.

A bit in the status parameter int_status will be set to 1'b1 to indicate the type of error.

The interrupt is cleared by writing to the interrupt acknowledge parameter int_ack. Setting

1'b1 a bit in the int_ack parameter will trigger the same bit in the int_status parameter to be

cleared to 1'b0. Please refer to Section 6.5 for more information on the interrupt parameters.

6.3.4

Arbiter

From the port interface blocks, commands are presented to the arbiter, which is responsible

for arbitrating between the port requests and sending a single command to the MPMC core.

6.3.5

Write data queue

The WRITE data queue is a WRITE data storage array for transactions. The queue consists

of multiple buffers holding WRITE data for the write requests of a particular port. Write data

is stored in these buffers for commands in the command queue until the command is

processed in the placement logic and needed by the DRAM command arbitration logic. The

buffers can accept data until space is no longer available. The buffers are defined to hold 16

entries.

The size of the WRITE data buffers and the burst length programmed into the memory

devices affect the overall performance of a single port during the WRITE operation. Each

buffer must have a depth of at least twice the number of data words for a memory burst to

ensure that the memory controller can continuously burst WRITE data for a port. The buffer

should also be so large to hold enough words to consume data for a single write transaction

related to the bus. The data may actually be written into the buffers from the bus at a later

time, depending on the priority of the request and the number of transactions in the

Command Queue.

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