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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0319 датащи(PDF) 54 Page - STMicroelectronics |
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RM0319 датащи(HTML) 54 Page - STMicroelectronics |
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54 / 368 page  Multiport DDR controller (MPMC) RM0319 54/368 Doc ID 022640 Rev 3 6 Multiport DDR controller (MPMC) This chapter focuses on MPMC functionality and operation. For technical details about the programmable registers related to the MPMC, refer to the MPMC registers in the following companion document: ● RM0321: SPEAr320S address map and registers 6.1 Overview MPMC is a high performance multiport memory controller able to support Mobile DDR and DDR2 double data rate memory devices. The multiport architecture ensures memory is shared efficiently among different high-bandwidth client modules. It offers 6 internal ports. One of them is reserved to register access during the controller initialization while the other five are used to access the external memory. It also includes the physical layer (PHY) and some DLL that allow a fine tuning of all the timing parameter to maximize the data valid windows at every frequency in the allowed range. |
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