RM0319 datasheet(57/368 Pages) STMICROELECTRONICS

57 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

57/368

queue of the core controller, and a single read data interface back from the core controller to

the port interface blocks. The architecture of the multiport system is shown in Figure 16.

Figure 16.

Memory controller architecture

The interface blocks contain FIFOs for commands, READ and WRITE data, handling any

clock domain crossings as required. From the port interface blocks, commands are

processed by an arbiter which feeds single commands to the command queue of the

memory controller core. WRITE and READ data are routed directly to the WRITE and

READ data queues of the memory controller core, arbiter independently.

Each port has a distinct WRITE data interface to the WRITE data queue of the memory

controller core. However, for READ data, all ports share a single READ data interface back

to the port interface blocks.

6.3.1

AHB memory controller interfaces

The memory controller core interfaces with 5 AHB data ports and 1 AHB register port. The

AHB data ports function as AHB slaves to external AHB masters such as CPUs, DMAs and

other peripherals. The port implementation is restricted to support the AHB-lite protocol and

is designed for multilayer AHB architectures. This implies that an AHB slave port will never

respond with a SPLIT or a RETRY response type. Early termination of AHB bursts is fully

supported.

Note:

An AHB slave port can be used in a system with masters that support the full AHB protocol

as long as the system is multilayer AHB.

The AHB memory controller interfaces handle all communication between the AHB bus and

the memory controller core. An incoming AHB transaction is first synchronized from the

AHB clock domain to the core clock domain, then mapped into a core-level transaction, and

finally stored in the AHB port FIFOs. From the AHB FIFOs, the transaction is presented to

the arbiter which arbitrates requests from all ports and forwards a single transaction to the

core.

AHB0

AHB1

AHB2

AHB3

AHB4

Placement

Logic

Port queue

Arbiter

Write data

queue

Command

queue

Read data

queue

CFG

REG

DRAM

Command

Logic

AHB-CFG

PHY

CORE Controller

AHB Port I/

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