RM0319 datasheet(164/368 Pages) STMICROELECTRONICS

164 / 368 page

Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

164/368

Doc ID 022640 Rev 3

For a properly working Ethernet system there should be no excessive length frames or

frames greater than 128 bytes with CRC/FCS errors. Collision fragments will be less than

128 bytes long. Therefore it will be a rare occurrence to find a frame fragment in a receive

buffer.

If bit zero is set when the receive buffer manager reads the location of the receive buffer,

then the buffer has already been used and cannot be used again until software has

processed the frame and cleared bit zero. In this case, the DMA block will set the buffer not

available bit in the receive status register and trigger an interrupt.

If bit zero is set when the receive buffer manager reads the location of the receive buffer and

a frame is being received, the frame will be discarded and the receive resource error

statistics register will be incremented.

A receive overrun condition occurs when either the AHB or ASB bus was not granted in time

or because HRESP was not OK. In a receive overrun condition, the receive overrun interrupt

is asserted and the buffer currently being written is recovered. The next frame that is

received whose address is recognized reuses the buffer.

If bit 17 of the network configuration register is set, the FCS of received frames shall not be

copied to memory. The frame length indicated in the receive status field shall be reduced by

four bytes in this case.

Transmit buffer

Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be

between 0 and 2047 bytes long, so it is possible to transmit frames longer than the

maximum length specified in IEEE std 802.3. Zero length buffers are allowed. The maximum

number of buffers permitted for each transmit frame is 128.

The start location for each transmit buffer is stored in memory in a list of transmit buffer

descriptors at a location pointed to by the transmit buffer queue pointer register. Each list

entry consists of two words. The first being the byte address of the transmit buffer and the

second containing the transmit control and status. Frames can be transmitted with or without

automatic CRC generation. If CRC is automatically generated, the pad will also be

automatically generated to take frames to a minimum length of 64 bytes.

Table 55: Transmit buffer descriptor entry defines an entry in the transmit buffer descriptor

list.

To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte

address to bits 31 to 0 in the first word of each list entry. The second transmit buffer

descriptor is initialized with control information that indicates the length of the buffer,

whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the

frame.

After transmission the control bits are written back to the second word of the first buffer

along with the used bit and other status information. Bit 31 is the used bit which must be

zero when the control word is read if transmission is to happen. It is written to one when a

frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit

30 is the wrap bit which can be set for any buffer within a frame. If no wrap bit is encountered

after 1024 descriptors the queue pointers rolls over to the start in a similar fashion to the

receive queue.

The transmit buffer queue pointer register must not be written while transmit is active. If a

new value is written to the transmit buffer queue pointer register the queue pointer resets

itself to point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of

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