RM0319 datasheet(166/368 Pages) STMICROELECTRONICS

166 / 368 page

Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

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Doc ID 022640 Rev 3

Transmit block

This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD

protocol.

Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from

the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If bit rate

is selected, the data is serialized and transmitted least significant bit first.

If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated as a

32 bit polynomial. This is inverted and appended to the end of the frame taking the frame

length to a minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer

descriptor of a transmit frame neither pad nor CRC are appended.

In full duplex mode frames are transmitted immediately. Back to back frames are transmitted

at least 96 bit times apart to guarantee the interframe gap.

In half duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to

deassert and then starts transmission after the interframe gap of 96 bit times. If the collision

signal is asserted during transmission, the transmitter will transmit a jam sequence of 32

bits taken from the data register and then retry transmission after the back off time has

elapsed.

The back off time is based on an XOR of the 10 least significant bits of the data coming from

the transmit FIFO and a 10 bit pseudo random number generator. The number of bits used

depends on the number of collisions seen. After the first collision 1 bit is used, the second 2,

and so on up to 10. Above 10, all 10 bits are used. An error will be indicated and no further

attempts will be made if 16 attempts cause collisions. This complies with the description in

Clause 4.2.3.2.5 of the IEEE 802.3 standard of the truncated binary exponential back off

algorithm.

If transmit DMA underruns or tx_r_err is asserted on the FIFO interface, bad CRC is

automatically appended using the same mechanism as jam insertion and the tx_er signal is

asserted. For a properly configured system this should never happen.

If the back pressure bit is set in the network control register in half duplex mode, the transmit

block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit rate mode 64

1s, whenever it sees an incoming frame to force a collision. This provides a way of

implementing flow control in half duplex mode.

[26:17]

Reserved

[16]

No CRC - when set no CRC will be appended to the current frame. This bit only

needs to be set for the last buffer of a frame.

[15]

Last buffer - when set this bit will indicate the last buffer in the current frame has been

reached

[14:11]

Reserved

[10:00]

Length of buffer

Table 55.

Transmit buffer descriptor entry

Bit

Function

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