RM0319 datasheet(162/368 Pages) STMICROELECTRONICS

162 / 368 page

Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

162/368

Doc ID 022640 Rev 3

location pointed to by the receive buffer queue pointer register. The receive buffer start

location is a word address. For the first buffer of a frame, the start location can be offset by

up to three bytes depending on the value written to bits 14 and 15 of the network

configuration register. If the start location of the buffer is offset the available length of the first

buffer of a frame is reduced by the corresponding number of bytes.

Each list entry consists of two words. The first being the address of the receive buffer and

the second being the receive status. If the length of a receive frame exceeds the buffer

length the status word for the used buffer is written with zeroes except for the start of frame

bit and the offset bits if appropriate. Bit zero of the address field is written to one to show the

buffer has been used. The receive buffer manager then reads the location of the next

receive buffer and fills that with receive frame data. The final buffer descriptor status word

contains the complete frame status. The received frame length is only available in the status

word of the final buffer descriptor. Refer to the following table for details of the receive buffer

descriptor list.

Table 54.

Receive buffer descriptor entry

Bit

Function

Word 0

[31:02]

Address of beginning of buffer

[01]

Wrap - marks last descriptor in receive buffer descriptor list.

[00]

Ownership - needs to be zero for the MACB to write data to the receive buffer. The

MACB sets this to one once it has successfully written a buffer to memory. Software

has to clear this bit before the buffer can be used again.

Word 1

[31]

Global all ones broadcast address detected

[30]

Multicast hash match

[29]

Unicast hash match

[28]

External address match

[27]

Unknown source address (reserved for future use)

[26]

Specific address register 1 match

[25]

Specific address register 2 match

[24]

Specific address register 3 match

[23]

Specific address register 4 match

[22]

Type ID match

[21]

VLAN tag detected (that is. type ID of 0x8100)

[20]

Priority tag detected (that is. type ID of 0x8100 and null VLAN identifier)

[19:17]

VLAN priority (only valid if bit 21 is set)

[16]

Concatenation format indicator (CFI) bit (only valid if bit 21 is set)

[15]

End of frame - when set the buffer contains the end of a frame. If end of frame is not

set then the only other valid status are bits 12, 13 and 14.

[14]

Start of frame - when set the buffer contains the start of a frame. If both bits 15 and

14 are set then the buffer contains a whole frame.

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