RM0319 datasheet(168/368 Pages) STMICROELECTRONICS

168 / 368 page

Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

168/368

Doc ID 022640 Rev 3

Pause frame transmission will happen immediately if transmit is inactive or if transmit is

active between the current frame and the next frame due to be transmitted. The transmitted

pause frame will comprise the items in the following list:

●

A destination address of 01-80-C2-00-00-01

●

A source address taken from the specific address 1 register

●

A type ID of 88-08 (MAC control frame)

●

A pause opcode of 00-01

●

A pause quantum

●

Fill of 00 to take the frame to minimum frame length

●

Valid FCS.

The pause quantum used in the generated frame will depend on the trigger source for the

frame as follows:

If bit 11 is written with a one, the pause quantum will come from the transmit pause

quantum register. The transmit pause quantum register resets to a value of 0xFFFF

giving a maximum pause quantum as a default.

If bit 12 is written with a one, the pause quantum will be zero.

If the tx_pause input is toggled and the tx_pause_zero input is held low until the next

toggle, the pause quantum will come from the transmit pause quantum register.

If the tx_pause input is toggled and the tx_pause_zero input is held high until the next

toggle, the pause quantum will be zero.

After transmission, no interrupts will be generated and the only statistics register that will be

incremented will be the pause frames transmitted register.

Receive block

The receive block checks for valid preamble, FCS, alignment and length, presents received

frames to the DMA block or FIFO interface and stores the frames destination address for

use by the address checking block.

If, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame

indication is sent to the DMA block. The DMA block then ceases sending data to memory,

but the FIFO interface, if present, continues sending data until the end of the frame is

reached when it asserts rx_w_err with rx_w_eop.

At the end of frame reception the receive block indicates to the DMA block whether the

frame is good or bad. The DMA block recovers the current receive buffer if the frame was

bad.

The receive block signals the register block to increment the alignment error, the CRC (FCS)

error, the short frame, long frame, jabber error, the receive symbol error statistics and the

length field mismatch statistics.

The enable bit for jumbo frames in the network configuration register allows the MACB to

receive jumbo frames of up to 10,240 bytes in size. This operation does not form part of the

IEEE 802.3 specification and is disabled by default. When jumbo frames are enabled,

frames received with a frame size greater than 10,240 bytes are discarded.

Address checking block

The address checking (or filter) block indicates to the DMA block which receive frames

should be copied to memory. The DMA block only copies frames that are addressed

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