RM0319 datasheet(161/368 Pages) STMICROELECTRONICS

161 / 368 page

RM0319

Fast Ethernet ports (RMII0/RMII1/MII1)

Doc ID 022640 Rev 3

161/368

data according to the CSMA/CD (carrier sense multiple access with collision detect)

protocol. The start of transmission is deferred if CRS (carrier sense) is active. If COL

(collision) becomes active during transmission, a jam sequence is asserted and the

transmission is retired after a random back off. CRS and COL have no effect in full duplex

mode.

13.4.5

DMA interface

The DMA interface contains receive and transmit FIFOs for buffering frame data. It loads the

transmit FIFO and empties the receive FIFO using AHB bus master operations. Receive

data is not sent to memory until the address checking logic has determined that the frame

should be copied.

Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed

length of 128 bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to

128 buffers are permitted per frame. The DMA block manages transmit and receive frame-

buffer queues. These queues can hold multiple frames.

All transfers are 32-bit words and may be single accesses or bursts of 2, 3 or 4 words. Burst

accesses do not cross sixteen byte boundaries. Bursts of 4 words are the default data

transfer, single accesses or bursts of less than four words may be used to transfer data at

the beginning or the end of a buffer.

The DMA controller performs six types of operation on the AHB bus. In order of priority

these are:

●

Receive buffer manager write

●

Receive buffer manager read

●

Transmit data

●

DMA read

●

Receive data DMA write

●

Transmit buffer manager read

●

Transmit buffer manager write

FIFOs

The receive and transmit FIFO depths are both set to eight words (32 bytes). Data is

typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus

request is asserted when the FIFO contains four words and has space for three more.

For transmit, a bus request is generated when there is space for four words, or when there is

space for two words if the next transfer is to be only one or two words.

Transmit buffers are permitted to be any length between zero and 2047 bytes. For short

lengths adequate bandwidth must be allowed for buffer management overhead. It is

recommended to perform simulations to ensure the system has adequate bandwidth if

transmit frames are likely to contain a number of very short buffers. If the DMA block cannot

access transmit data from memory in time “transmit underrun" status will be reported and an

interrupt asserted.

Receive buffer

Received frames, optionally including CRC/FCS, are written to receive buffers stored in

memory. Each receive buffer is 128 bytes long, this number is parameterizable. The start

location for each receive buffer is stored in memory in a list of receive buffer descriptors at a

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