RM0319 datasheet(163/368 Pages) STMICROELECTRONICS

163 / 368 page

RM0319

Fast Ethernet ports (RMII0/RMII1/MII1)

Doc ID 022640 Rev 3

163/368

To receive frames, the buffer descriptors must be initialized by writing an appropriate

address to bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero.

Bit one is the wrap bit and indicates the last entry in the list.

The start location of the receive buffer descriptor list must be written to the receive buffer

queue pointer register before setting the receive enable bit in the network control register to

enable receive. As soon as the receive block starts writing the received frame data to the

receive FIFO, the receive buffer manager reads the first receive buffer location pointed to by

the receive buffer queue pointer register.

If the filter block indicates that the frame should be copied to memory, the receive data DMA

operation starts writing data into the receive buffer. If an error occurs, the buffer is

recovered.

If the current buffer pointer has its wrap bit set or is the 1024th descriptor, the next receive

buffer location is read from the beginning of the receive descriptor list. Otherwise, the next

receive buffer location is read from the next word in memory.

There is an 11 bit counter to count out the 2048 word locations of a maximum length,

receive buffer descriptor list. This is added with the value originally written to the receive

buffer queue pointer register to produce a pointer into the list. A read of the receive buffer

queue pointer register returns the pointer value, which is the queue entry currently being

accessed.

The counter is reset after receive status is written to a descriptor that has its wrap bit set or

rolls over to zero after 1024 descriptors have been accessed. The value written to the

receive buffer pointer register may be any word-aligned address, provided that there are at

least 2048 word locations available between the pointer and the top of the memory.

As receive buffer manager writes are bursts of two words, to ensure that this does not occur

it is best to write the pointer register with the least three significant bits set to zero.

As receive buffers are used, the receive buffer manager sets bit zero of the first word of the

descriptor to indicate used. If a receive error is detected the receive buffer currently being

written will be recovered. Previous buffers will not be recovered.

Software should search through the used bits in the buffer descriptors to find out how many

frames have been received. It should be checking the start-of-frame and end-of-frame bits,

and not rely on the value returned by the receive buffer queue pointer register which

changes continuously as more buffers are used.

For CRC errored frames, excessive length frames or length field mismatched frames, all of

which are counted in the statistics registers, it is possible that a frame fragment might be

stored in a sequence of receive buffers. Software can detect this by looking for start of frame

bit set in a buffer following a buffer with no end of frame bit set.

[13:12]

Receive buffer offset - indicates the number of bytes by which the data in the first

buffer is offset from the word address. Updated with the current values of the

network configuration register. If jumbo frame mode is enabled through bit 3 of the

network configuration register, then bits 13:12 of the receive buffer descriptor entry

are used to indicate bits 13:12 of the frame length.

[11:00]

Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame

mode is selected.

Table 54.

Receive buffer descriptor entry (continued)

Bit

Function

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