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RM0319 датащи(PDF) 160 Page - STMicroelectronics |
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RM0319 датащи(HTML) 160 Page - STMicroelectronics |
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160 / 368 page ![]() Fast Ethernet ports (RMII0/RMII1/MII1) RM0319 160/368 Doc ID 022640 Rev 3 13.4 Functional description The MACB module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. Figure 53. MACB detailed block diagram 13.4.1 Address checker The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. 13.4.2 Statistics register block The statistics register block contains registers for counting various types of event associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with IEEE 802.3 Clause 30. 13.4.3 Control registers The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of operation such as full or half duplex. 13.4.4 Receive block The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address checking block and DMA interface. The transmit block takes data from the DMA interface adds preamble and, if necessary, pad and FCS, and transmits Q Q SET CLR D Q Q SET CLR D pclk_syncs Q Q SET CLR D Q Q SET CLR D hclk_syncs Statistics Register Control Registe r DMA Interface Tx FIFO Rx FIFO MII/RMII External FIFO interface DMA I/F MDIO CPU I/F FIFO Interface Address Checker Ethernet Receive Ethernet Transmit Tx-State Machine MII/RMII |
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