RM0319 datasheet(167/368 Pages) STMICROELECTRONICS

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RM0319

Fast Ethernet ports (RMII0/RMII1/MII1)

Doc ID 022640 Rev 3

167/368

Pause Frame Support

Note:

See Clause 31, Annex 31A and 31B of IEEE standard 802.3 for a full specification of the

pause operation.

The start of an 802.3 pause frame looks like this:

The network configuration register contains a receive pause enable bit (13). If a valid pause

frame is received the pause time register is updated with the frame's pause time regardless

of its current contents and regardless of the state of the configuration register bit 13. An

interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the

interrupt mask register. If bit 13 is set in the network configuration register and the value of

the pause time register is non-zero, no new frame is transmitted until the pause time register

has decremented to zero.

The loading of a new pause time, and hence the pausing of transmission, only occurs when

the MACB is configured for full duplex operation. If the MACB is configured for half duplex

there will be no transmission pause, but the pause frame received interrupt will still be

triggered.

A valid pause frame is defined as having a destination address that matches either the

address stored in specific address register 1 or matches 0x0180C2000001 and has the

MAC control frame type ID of 0x8808 and has the pause opcode of 0x0001. Pause frames

that have FCS or other errors will be treated as invalid and will be discarded. Valid pause

frames received will increment the pause frame received statistic register.

The pause time register decrements every 512 bit times (that is. 128 rx_clks in nibble mode)

once transmission has stopped. For test purposes the register decrements every rx_clk

cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration

decrementing will happen regardless of whether transmission has stopped or not.

An interrupt (13) is asserted whenever the pause time register decrements to zero

(assuming it is enabled in the interrupt mask register).

Automatic transmission of pause frames is supported through the transmit pause frame bits

of the network control register and the tx_pause and tx_pause_zero inputs.

If either bit 11 or bit 12 of the network control register is written to with a 1, or if the input

signal tx_pause is toggled, a pause frame will be transmitted only if full duplex is selected in

the network configuration register and transmit is enabled in the network control register.

Table 56.

Pause frame support

Destination

Address

Source Address

Type (MAC

Control Frame)

Pause opcode

Pause Time

0x0180C2000001

6 bytes

0x8808

0x0001

2 bytes

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