ADuC7023BCBZ62I-R7 datasheet(89/96 Pages) AD

89 / 96 page

Data Sheet

ADuC7023

| Page 89 of 96

GROUNDING AND BOARD LAYOUT

RECOMMENDATIONS

As with all high resolution data converters, special attention

must be paid to grounding and PC board layout of the

ADuC7023-based designs to achieve optimum performance

from the ADCs and DACs.

Although the parts have separate pins for analog and digital ground

(AGND and DGND), the user must not tie these to two separate

ground planes unless the two ground planes are connected very

close to the part. This is illustrated in the simplified example

shown in Figure 50a. In systems where digital and analog ground

planes are connected together somewhere else (at the system

power supply, for example), the planes cannot be reconnected

near the part because a ground loop would result. In these cases, tie

all the ADuC7023 AGND and DGND pins to the analog ground

plane, as illustrated in Figure 50b. In systems with only one ground

plane, ensure that the digital and analog components are physically

separated onto separate halves of the board so that digital return

currents do not flow near analog circuitry (and vice versa).

The ADuC7023 can then be placed between the digital and

analog sections, as illustrated in Figure 50c.

PLACE ANALOG

COMPONENTS HERE

PLACE DIGITAL

COMPONENTS HERE

AGND

DGND

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS HERE

AGND

DGND

PLACE ANALOG

COMPONENTS HERE

PLACE DIGITAL

COMPONENTS HERE

DGND

Figure 50. System Grounding Schemes

In all of these scenarios, and in more complicated real-life

applications, users should pay particular attention to the flow of

current from the supplies and back to ground. Make sure the return

paths for all currents are as close as possible to the paths the

currents took to reach their destinations.

For example, do not power components on the analog side (as

seen in Figure 50b) with IOVDD because that would force return

currents from IOVDD to flow through AGND. Avoid digital

currents flowing under analog circuitry, which can occur if a

noisy digital chip is placed on the left half of the board (shown

in Figure 50c). If possible, avoid large discontinuities in the

ground plane(s) such as those formed by a long trace on the same

layer, because they force return signals to travel a longer path.

In addition, make all connections to the ground plane directly,

with little or no trace separating the pin from its via to ground.

When connecting fast logic signals (rise/fall time < 5 ns) to any of

the ADuC7023 digital inputs, add a series resistor to each

relevant line to keep rise and fall times longer than 5 ns at the

input pins of the part. A value of 100 Ω or 200 Ω is usually

sufficient enough to prevent high speed signals from coupling

capacitively into the part and affecting the accuracy of ADC

conversions.

CLOCK OSCILLATOR

The clock source for the ADuC7023 can be generated by the

internal PLL or by an external clock input. To use the internal

PLL, connect a 32.768 kHz parallel resonant crystal between

XCLKI and XCLKO, and connect a capacitor from each pin to

ground, as shown in Figure 51. The crystal allows the PLL to lock

correctly to give a frequency of 41.78 MHz. If no external crystal

is present, the internal oscillator is used to give a typical

frequency of 41.78 MHz ± 3%.

ADuC7023

INTERNAL

PLL

12pF

XCLKI

32.768kHz

12pF

XCLKO

Figure 51. External Parallel Resonant Crystal Connections

To use an external source clock input instead of the PLL (see

Figure 52), Bit 1 and Bit 0 of PLLCON must be modified. The

external clock uses P1.1 and XCLK.

ADuC7023

FREQUENCY

DIVIDER

XCLKO

XCLKI

XCLK

EXTERNAL

CLOCK

SOURCE

Figure 52. Connecting an External Clock Source

Using an external clock source, the ADuC7023 specified

operational clock speed range is 50 kHz to 44 MHz ± 1%, which

ensures correct operation of the analog peripherals and Flash/EE.

Rev. E

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