ADuC7023BCBZ62I-R7 datasheet(55/96 Pages) AD

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Data Sheet

ADuC7023

| Page 55 of 96

Table 63. SPISTA MMR Bit Designations

Bit

Name

Description

15 to 12

Reserved bits.

SPIREX

SPI Rx FIFO excess bytes present.

This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON

This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE.

10 to 8

SPIRXFSTA[2:0]

SPI Rx FIFO status bits.

[000] = Rx FIFO is empty.

[001] = 1 valid byte in the FIFO.

[010] = 2 valid byte in the FIFO.

[011] = 3 valid byte in the FIFO.

[100] = 4 valid byte in the FIFO.

SPIFOF

SPI Rx FIFO overflow status bit.

This bit is set when the Rx FIFO is full when new data is loaded to the FIFO. This bit generates an interrupt

except when SPIRFLH is set in SPICON.

This bit is cleared when the SPISTA register is read.

SPIRXIRQ

SPI Rx IRQ status bit.

This bit is set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the

required number of bytes have been received.

This bit is cleared when the SPISTA register is read.

SPITXIRQ

SPI Tx IRQ status bit.

This bit is set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required

number of bytes have been transmitted.

This bit is cleared when the SPISTA register is read.

SPITXUF

SPI Tx FIFO underflow.

This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt

except when SPITFLH is set in SPICON.

This bit is cleared when the SPISTA register is read.

3 to 1

SPITXFSTA[2:0]

SPI Tx FIFO status bits.

[000] = Tx FIFO is empty.

[001] = 1 valid byte in the FIFO.

[010] = 2 valid byte in the FIFO.

[011] = 3 valid byte in the FIFO.

[100] = 4 valid byte in the FIFO.

SPIISTA

SPI interrupt status bit.

This bit is set to 1 when an SPI based interrupt occurs.

This bit is cleared after reading SPISTA.

SPIRX Register

Name:

SPIRX

Address:

0xFFFF0A04

Default value: 0x00

Access:

Read

Function:

This 8-bit MMR is the SPI receive register.

SPITX Register

Name:

SPITX

Address:

0xFFFF0A08

Default value: 0xXX

Access:

Write

Function:

This 8-bit MMR is the SPI transmit register.

Rev. E

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