ADuC7023BCBZ62I-R7 datasheet(68/96 Pages) AD

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ADuC7023

Data Sheet

| Page 68 of 96

Table 77. PLAELMx MMR Bit Descriptions

Bit

Value

Description

31 to 11

Reserved.

10 to 9

Mux 0 control (see Table 81).

8 to 7

Mux 1 control (see Table 81).

Mux 2 control.

This bit is set by the user to select the

output of Mux 0.

This bit is cleared by the user to select the

bit value from the PLADIN register.

Mux 3 control.

This bit is set by the user to select the

input pin of the particular element.

This bit is cleared by the user to select the

output of Mux 1.

4 to 1

Look-up table control.

0000

0001

NOR.

0010

B and not A.

0011

Not A.

0100

A and not B.

0101

Not B.

0110

EXOR.

0111

NAND.

1000

AND.

1001

EXNOR.

1010

1011

Not A or B.

1100

1101

A or not B.

1110

OR.

1111

Mux 4 control.

This bit is set by the user to bypass the flip-

flop.

This bit is cleared by the user to select the

flip-flop (cleared by default).

PLACLK Register

Name:

PLACLK

Address:

0xFFFF0B40

Default value:

0x00

Access:

Read/write

Function:

PLACLK is the clock selection for the flip-

flops. The maximum frequency when using

the GPIO pins as the clock input for the PLA

blocks is 41.78 MHz.

Table 78. PLACLK MMR Bit Descriptions

Bit

Value

Description

31 to 7

Reserved.

6 to 4

Clock source selection.

000

GPIO clock on P0.5.

001

GPIO clock on P1.1.

010

GPIO clock on P1.6.

011

HCLK.

100

External 32.768 kHz crystal.

101

Timer1 overflow.

110

UCLK.

111

Internal 32,768 oscillator.

Reserved.

2 to 0

Clock source selection.

000

GPIO clock on P0.5.

001

GPIO clock on P1.1.

010

GPIO clock on P1.6.

011

HCLK.

100

External 32.768 kHz crystal.

101

Timer1 overflow.

110

UCLK.

111

Internal 32,768 oscillator.

Rev. E

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