ADuC7023BCBZ62I-R7 datasheet(76/96 Pages) AD

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ADuC7023

Data Sheet

| Page 76 of 96

PROCESSOR REFERENCE PERIPHERALS

INTERRUPT SYSTEM

There are 22 interrupt sources on the ADuC7023 that are

controlled by the interrupt controller. Most interrupts are

generated from the on-chip peripherals, such as ADC. Four

additional interrupt sources are generated from external interrupt

request pins, IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI

CPU core only recognizes interrupts as one of two types, a

normal interrupt request IRQ or a fast interrupt request FIQ.

All the interrupts can be masked separately.

The control and configuration of the interrupt system is managed

through nine interrupt related registers, four dedicated to IRQ,

and four dedicated to FIQ. An additional MMR is used to select

the programmed interrupt source. The bits in each IRQ and

FIQ registers represent the same interrupt source as described

in Table 88.

The ADuC7023 contains a vectored interrupt controller (VIC)

that supports nested interrupts up to eight levels. The VIC also

allows the programmer to assign priority levels to all interrupt

sources. Interrupt nesting is enabled by setting the ENIRQN bit

in the IRQCONN register. A number of extra MMRs are used

when the full-vectored interrupt controller is enabled.

IRQSTA/FIQSTA should be saved immediately upon entering

the interrupt service routine (ISR) to ensure that all valid

interrupt sources are serviced.

Table 88. IRQ/FIQ MMRs Bit Description

Bit

Description

All interrupts OR’ed (FIQ only).

SWI.

Timer0.

Timer1.

Watchdog timer (Timer 2).

Flash control.

ADC channel.

PLL lock.

I2C0 master.

I2C0 slave.

I2C1 master.

I2C1 slave.

SPI.

External IRQ0.

Comparator.

PSM.

External IRQ1.

PLA IRQ0.

External IRQ2.

External IRQ3.

PLA IRQ1.

PWM.

IRQ

The interrupt request (IRQ) is the exception signal to enter the

IRQ mode of the processor. It is used to service general-purpose

interrupt handling of internal and external events.

The four 32-bit registers dedicated to IRQ are: IRQSTA, IRQSIG,

IRQEN, and IRQCLR.

IRQSTA Register

Name:

IRQSTA

Address:

0xFFFF0000

Default value:

0x00000000

Access:

Read

Function:

IRQSTA (read-only register) provides the

current-enabled IRQ source status. When

set to 1, that source generates an active IRQ

request to the ARM7TDMI core. There is no

priority encoder or interrupt vector

generation. This function is implemented in

software in a common interrupt handler

routine. All 32 bits are logically OR’ed to

create the IRQ signal to the ARM7TDMI

core.

IRQSIG Register

Name:

IRQSIG

Address:

0xFFFF0004

Default value:

0x00XXX000

Access:

Read

Function:

IRQSIG reflects the status of the different IRQ

sources. If a peripheral generates an IRQ

signal, the corresponding bit in the IRQSIG is

set; otherwise, it is cleared. The IRQSIG bits

are cleared when the interrupt in the

particular peripheral is cleared. All IRQ

sources can be masked in the IRQEN MMR.

IRQSIG is read-only.

Rev. E

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