ADuC7023BCBZ62I-R7 datasheet(84/96 Pages) AD

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ADuC7023

Data Sheet

| Page 84 of 96

The Timer0 interface consists of four MMRs: T0LD, T0VAL,

T0CON, and T0CLRI.

T0LD Register

Name:

T0LD

Address:

0xFFFF0300

Default value:

0x0000

Access:

Read/write

T0LD is a 16-bit load register that holds the 16-bit value that is

loaded into the counter.

T0VAL Register

Name:

T0VAL

Address:

0xFFFF0304

Default Value:

0xFFFF

Access:

Read

T0VAL is a 16-bit read-only register representing the current

state of the counter.

T0CON Register

Name:

T0CON

Address:

0xFFFF0308

Default value:

0x0000

Access:

R/W

T0CON is the configuration MMR described in Table 102.

Table 102. T0CON MMR Bit Descriptions

Bit

Value

Description

15 to 8

Reserved.

Timer0 enable bit.

This bit is set by the user to enable Timer0. This

bit is cleared by the user to disable Timer0 by

default.

Timer0 mode.

This bit is set by the user to operate in

periodic mode.

This bit is cleared by the user to operate in

free-running mode. Default mode.

5 to 4

Clock select bits.

HCLK.

UCLK.

Internal 32768 Hz oscillator.

Reserved.

3 to 2

Source clock/1. Default value.

Source clock/16.

Source clock/256.

Undefined. Equivalent to 00.

1 to 0

Reserved.

T0CLRI Register

Name:

T0CLRI

Address:

0xFFFF030C

Default value:

0xXX

Access:

Write

T0CLRI is an 8-bit register. Writing any value to this register

clears the interrupt.

The following is the recommended procedure for servicing the

Timer 0 interrupt:

void

IRQ_Handler(void) __irq

{

if(IRQSTA & BIT2) // Timer0 IRQ?

{

T0CLRI = 0;

//clear Timer0 interrupt

T0CON = 0x00; //disable Timer0 interrupt

T0CON = 0xC8; //enable Timer0 interrupt

}

Timer1 (General-Purpose Timer)

Timer1 is a general-purpose, 32-bit timer (count down or count

up) with a programmable prescaler. The source can be the 32 kHz

external crystal, the undivided system, the core clock, or P1.1

(maximum frequency 44 MHz). This source can be scaled by a

factor of 1, 16, 256, or 32,768.

The counter can be formatted as a standard 32-bit value or as

hours, minutes, seconds, hundredths.

Timer1 has a capture register (T1CAP) that can be triggered by

a selected IRQ source initial assertion. This feature can be used

to determine the assertion of an event more accurately than the

precision allowed by the RTOS timer when the IRQ is serviced.

Timer1 can be used to start ADC conversions as shown in the

block diagram in Figure 43.

32kHz OSCILLATOR

HCLK

UCLK

P1.1

IRQ[19:0]

PRESCALER

/1, 16, 256,

OR 32,768

32-BIT

UP/DOWN

COUNTER

32-BIT

LOAD

TIMER1

VALUE

CAPTURE

TIMER1 IRQ

ADC CONVERSION

Figure 43. Timer1 Block Diagram

The Timer1 interface consists of five MMRs: T1LD, T1VAL,

T1CON, T1CLRI, and T1CAP.

Rev. E

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