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ADuC7023BCBZ62I-R7 датащи(PDF) 70 Page - Analog Devices |
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ADuC7023BCBZ62I-R7 датащи(HTML) 70 Page - Analog Devices |
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70 / 96 page ![]() ADuC7023 Data Sheet | Page 70 of 96 Table 80. Feedback Configuration Bit Value PLAELM0 PLAELM1 to PLAELM7 PLAELM8 PLAELM9 to PLAELM15 10 to 9 00 Element 15 Element 0 Element 7 Element 8 01 Element 2 Element 2 Element 10 Element 10 10 Element 4 Element 4 Element 12 Element 12 11 Element 6 Element 6 Element 14 Element 14 8 to 7 00 Element 1 Element 1 Element 9 Element 9 01 Element 3 Element 3 Element 11 Element 11 10 Element 5 Element 5 Element 13 Element 13 11 Element 7 Element 7 Element 15 Element 15 PLAADC Register Name: PLAADC Address: 0xFFFF0B48 Default value: 0x00000000 Access: Read/write Function: PLAADC is the PLA source for the ADC start conversion signal. Table 81. PLAADC MMR Bit Descriptions Bit Value Description 31 to 5 Reserved. 4 ADC start conversion enable bit. This bit is set by the user to enable ADC start conversion from PLA. This bit is cleared by the user to disable ADC start conversion from PLA. 3 to 0 ADC start conversion source. 0000 PLA Element 0. 0001 PLA Element 1. 0010 PLA Element 2. 0011 PLA Element 3. 0100 PLA Element 4. 0101 PLA Element 5. 0110 PLA Element 6. 0111 PLA Element 7. 1000 PLA Element 8. 1001 PLA Element 9. 1010 PLA Element 10. 1011 PLA Element 11. 1100 PLA Element 12. 1101 PLA Element 13. 1110 PLA Element 14. 1111 PLA Element 15. PLADIN Register Name: PLADIN Address: 0xFFFF0B4C Default value: 0x00000000 Access: Read/write Function: PLADIN is a data input MMR for PLA. Table 82. PLADIN MMR Bit Descriptions Bit Description 31 to 16 Reserved. 15 to 0 Input bit to Element 15 to Element 0. PLADOUT Register Name: PLADOUT Address: 0xFFFF0B50 Default value: 0x00000000 Access: Read Function: PLADOUT is a data output MMR for PLA. This register is always updated. Table 83. PLADOUT MMR Bit Descriptions Bit Description 31 to 16 Reserved. 15 to 0 Output bit from Element 15 to Element 0. PLALCK Register Name: PLALCK Address: 0xFFFF0B54 Default value: 0x00 Access: Write Function: PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure PLA. Rev. E |
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